I have a FPGA and a async-sram with OEn, WEn that I want to interface.

To protect against short circuit I want to set resistors on the data lines.

What is the value that would protect the FPGA and SRAM but would still leave the design functional?

  • Voltage level is 3.3, the FPGA is a Zync 7020 the SRAM is a IS61LV5128AL.
  • I want to transfer at 25-50Mhz.

Would i.e. 20 Ohm be sufficient to protect the FPGA and SRAM pads to get too hot in case they both try to drive the signal in opposite directions?

  • 4
    \$\begingroup\$ It is bad practice to adapt your circuit to be able to cope with design failures. The correct procedure is to simulate the FPGA code with a model of the memory and make sure the system works as it should be. Then implement it. \$\endgroup\$
    – Oldfart
    Jan 27, 2019 at 13:49
  • \$\begingroup\$ The SRAM is on a FMC extension card. When I forget to reprogram the FPGA before plugging the FMC card I might run into trouble. \$\endgroup\$ Jan 28, 2019 at 18:54

1 Answer 1


Start by looking at the maximum current both side can source and sink and choose your resistor to limit current flows to those values. However, as @Oldfart said, get the design right is preferable.


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