If a very large MOSFET (i.e. with a very wide channel) was implemented as a single physical device, like the one you saw in class, then the gate electrode would be very long and thin. This would cause a significant RC delay down the gate and so the MOSFET would turn on and off very slowly. Furthermore, it would be difficult to put such a device in a package because it would be hundreds or thousands of times wider than it was long.
So, it is electrically superior and easier to handle the MOSFET if you break it up into many small MOSFETs. The source, drain, and gate terminals of all of these small devices are connected in parallel. The result is the same as if you had built one huge device.
In CMOS VLSI design these small devices are often called the "fingers" and are actually drawn as parallel structures. Alternate fingers can then share their source/drain regions. Power MOSFETs use other techniques for forming the individual small devices.
Here's an example from the design of digital-to-analog converter:
The yellow layer is polysilicon, and the long vertical stripes are MOSFET gates. The red layer is metal, and the white squares are contacts from the metal down to either the poly gates or source/drain regions. In the top right you see a large PMOS transistor with five parallel gate fingers. In between the gate fingers are the source and drain regions, looks like three parallel sources and three parallel drains. Sharing the source/drain regions like this also reduces the capacitance of those structures to the substrate (N-well) underneath. The linked page has several examples of how this is used in the design of analog CMOS. My experience was mainly in digital devices, but we used the same idea when we needed a high-drive buffer for a global clock or an I/O pin.