# Altium vias on test point pads

I don't normally allow vias on regular SMT pads, but for test points there's no real need to go out of your way to avoid them. As long as the bed-o-nails will make good contact anyways.

Now I can write a clearance rule like this:

(Component Like 'TP*')


which matches Same Net Only and

IsVia OR IsTrack


This will allow you to plop down a via (p v) on top of the testpoint - It'll show a violation before you drop the via (since it's not connected to any net) but it disappears when it gets connected to the pad.