0
\$\begingroup\$

I don't normally allow vias on regular SMT pads, but for test points there's no real need to go out of your way to avoid them. As long as the bed-o-nails will make good contact anyways.

Now I can write a clearance rule like this:

(Component Like 'TP*')

which matches Same Net Only and

IsVia OR IsTrack 

This will allow you to plop down a via (p v) on top of the testpoint - It'll show a violation before you drop the via (since it's not connected to any net) but it disappears when it gets connected to the pad.

However, when routing, adding a via on TP pad, no go, nuh-uh. It'll get pushed outside the pad. I've tried adding a high speed rule about vias on SMD pads but it had no effect..

Is this just a limitation of the online DRC?

\$\endgroup\$
  • \$\begingroup\$ One reason not to put vias in test points: Contacting the test pad can break the connection between the outer layer copper and the plating in the via barrel, causing a connectivity failure (possibly latent) that doesn't reveal itself until after testing is completed (meaning, it's probably discovered by the customer, resulting in a field return). (Or at least, that was the reasoning at one place I worked for banning vias in test pads) \$\endgroup\$ – The Photon Jan 28 at 18:09
  • \$\begingroup\$ @ThePhoton I could buy poor connection if the probe doesn't hit the via in the middle i.e. you should use large drills. My TH test points are with 1mm drill and the test rig guys are happy with those. I worked for a company that insisted each and every net needs to have a TP, only exception was that if you've got e.g. resistors in series you can skip the middle one. Putting vias on testpoints directly was sometimes a necessity.. \$\endgroup\$ – Barleyman Jan 29 at 10:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.