When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm not sure what's causing this.
- I've checked
Design Rules > Polygon Connectand tried both Direct and Relief connect (no change). I don't think it's a relief because if it was it would encircle the via.
- On the polygon properties, I have tried turning on/off
Remove Dead Copper,
Remove Islands by Area, and
Remove Narrow Necks, but the gaps persist (albeit with some corner sharpness differences).
I put some vias near the edge of the poly to try and figure this out:
I suspect there may be a design rule affecting it, but I am not sure what to look for.
What should I check in Altium that controls gaps around/near vias on polygon pours of the same net?