When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm not sure what's causing this.

Gaps in polygon pour in Altium Designer

  • I've checked Design Rules > Polygon Connect and tried both Direct and Relief connect (no change). I don't think it's a relief because if it was it would encircle the via.
  • On the polygon properties, I have tried turning on/off Remove Dead Copper, Remove Islands by Area, and Remove Narrow Necks, but the gaps persist (albeit with some corner sharpness differences).

I put some vias near the edge of the poly to try and figure this out:

Gaps in polygon pour in Altium Designer, near edge

I suspect there may be a design rule affecting it, but I am not sure what to look for.

What should I check in Altium that controls gaps around/near vias on polygon pours of the same net?

  • \$\begingroup\$ What is the track size used in your pour polygons? Is it larger than one or more of your clearance constraints? \$\endgroup\$
    – brhans
    Commented Jan 28, 2019 at 18:07
  • \$\begingroup\$ @brhans Track width is 0.2mm. Clearance constraints are 0.152mm across the entire grid in that particular design rule. \$\endgroup\$
    – JYelton
    Commented Jan 28, 2019 at 18:08
  • 1
    \$\begingroup\$ I suspect that if you reduce the track size down below that clearance constraint then your gaps will disappear - but I forget exactly which rule is likely to be causing the issue ... it's been a few years since I last used Altium. \$\endgroup\$
    – brhans
    Commented Jan 28, 2019 at 18:11
  • \$\begingroup\$ @brhans I tried a few different clearance values to no avail. It may be worth noting that the clearance rules are set for "different nets only." Thanks for the advice however. \$\endgroup\$
    – JYelton
    Commented Jan 28, 2019 at 18:40
  • \$\begingroup\$ Going from memory here, but I think there is a per polygon option to 'pour over same net objects' in Altium that can help solve some of this. \$\endgroup\$
    – M D
    Commented Jan 28, 2019 at 18:59

1 Answer 1


Go to Design -> Rules, look for a Polygon Connect Rule (NOT a Plane connect rule).

In that rule, make sure that "Direct Connect" is selected. Confirm, then leave that dialog. Repour all polygons (T->G->A). Now, check if you can still see those holes.

I have a feeling that these come from a thermal relief connect (which is setup in said rule), overlapped by tracks.

  • \$\begingroup\$ That was indeed it, the PolygonConnect rule has a Connect Style option which was set to Relief Connect rather than Direct Connect. For through-hole pads (components and wires), the relief makes sense, but for vias connecting a top-layer trace to the polygon pour, the direct method seems correct. Thanks! \$\endgroup\$
    – JYelton
    Commented Jan 28, 2019 at 20:53
  • \$\begingroup\$ You nailed it Tom. \$\endgroup\$
    – Steve
    Commented Jan 28, 2019 at 21:15

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