I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra circuitry of self-test. Both the circuits are working fine.

My objective is to find out the resource overhead of the self-test circuit that is combined with the controller, on different xilinx platforms and devices.

The resource consumption of each circuit is shown in below:

enter image description here

  • Why is the area overhead of the same self-test circuit is different on different xilinx devices (23.88 % on spartan 3, 95.58% on spartan 6 and 34.02% on kintex 7)?
  • If the same controller and self-test variant of the controller is synthesized without any changes on differnet xilinx devices, then why is the overhead not of the same percentage?
  • why is the overhead is higher on newer devices?
  • \$\begingroup\$ Your data doesn't seem consistent. Your self-test circuitry added 2 flip-flops to the Spartan 3, 13 flip-flops to the Spartan 6, and 14 flip-flops to the Kintex. You need to look at the synthesis results for the self-test circuitry on those three platforms and determine why they are so different. \$\endgroup\$ – Elliot Alderson Jan 28 at 20:32
  • \$\begingroup\$ It's hard to say without seeing the code. However, you are using very different versions of the tool chain software to target these parts, it is entirely possible that the tools are doing very different things with the mapping of the design onto chip resources and as a result it's hard to make a reasonable comparison of the results. \$\endgroup\$ – alex.forencich Jan 29 at 0:42

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