Prevent design to power up when updating firmware in flash memory

Question

I have an FPGA based design using the MachXO2 by Lattice. I wanted a quick, easy and clean way to perform firmware updates, which are frequent, so I decided to use an external flash memory (AT25SF041 by Adesto) to store the bitstream and set the FPGA to configure itself using Master SPI Mode. The memory is used to supply the bitstream only, it's not used again after boot.

In order to perform a firmware update, the user has to:

1. Remove power from the device
2. Attach a provided cable in the corresponding socket
3. Update firmware using a dedicated application
4. Remove the cable and power the device

The socket essentially contains the SPI and power pins of the Flash Memory while the cable is a USB to SPI. The block diagram is depicted below:

As you may notice, when the cable is connected is going to fire up the entire device which is what I am trying to avoid. After consideration, I decided to use a diode between the Flash power pin and the main power supply, as depicted below:

According to the AT25SF041 datasheet, p.33, the Active Current when performing a reading operation below 20 MHz (FPGA uses 2.08 MHz) is typically around 3 mA. In the same page is mentioned that the IC will operate fine with a supply voltage between 2.5V - 3.6V.

A diode has a typical voltage drop of 0.7V, which results in a supply of 2.7V. Additionally, considering that the active current is so low, the drop will probably be a little bit reduced. Also by choosing a diode of a generally lower voltage drop things will be even better.

Based on the above, I did assemble a prototype employing a diode, and everything worked fine. I used two different diodes to verify that it works, a 1N4001 and a PH4148, and it worked with both of them. (Of course I will use a more appropriate diode in the final design)

My questions

1) Is this a sane solution? Although it works fine, I am still a little bit worried it may causing or might cause a problem which I am not aware.

2) The FPGA requires 2 pull-up resistors in order for Master SPI mode to operate. They are not required using the cable, but they are getting power. Is it a problem if a pull-up resistor is powered although it is not needed? I think not but I would like some verification on that. The cable I am using now, if it matters, is C232HM by FTDI, which utilizes a FT232H IC of the same company.

Any suggestions and alternatives are welcome. Thanks in advance!

Answer 1

It would be better to use a Schottky diode for this purpose, but there's another potential issue- the signals that are driving the flash memory will be driving the FPGA inputs with the Vcc approximately zero. My reading of at least this Mach02 datasheet is that this is permissible- and that it will not back feed the Mach02 Vcc. You can verify this by testing.

Assuming that this is not a problem, a suitable diode might be a 1N5817 or similar SMT part which will typically drop a couple hundred mV.

I don't see a problem with the pullups. You probably want to have a ceramic bypass capacitor right across the flash power pins.

Note: You could also implement the reset solution @Nake suggests- you may have to do a bit of work to create a reset input. This would be "cleaner", in my opinion.