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So this query is related to DC synthesis compiler for digital design.

I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters [name_of_params] only to the top level design or to each entity under it and specify the individual params?

Here's a link to my code snippet.

PS: if it's not clear, let me know; I will upload a screenshot then!

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    \$\begingroup\$ Specify the top-level generic/parameter, wherever it may be. If they trace/associate downward, you only need to specify at the top-level and they will override the associated defaults at any level below. yeh, as @ElliotAlderson says, you should try it both ways and prove it to yourself. Also, you can probably pass the values on the command line (you can in QuestaSim anyway.. not sure about DC) \$\endgroup\$ – CapnJJ Jan 28 at 20:33
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    \$\begingroup\$ Have you tried to do it both ways? \$\endgroup\$ – Elliot Alderson Jan 28 at 20:33
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    \$\begingroup\$ Hey, Kashif, it always pays to add as much info as possible without bloating the question, so: instead of adding a screenshot of text, use a service like gist.github.com to add longer code snippets (and link to that), or add shorter code directly to the question (and use the "code formatting" button to make it look like code). \$\endgroup\$ – Marcus Müller Jan 28 at 20:42
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    \$\begingroup\$ @MarcusMüller I added VHDL... and then thought to add Verilog at the same time. you can remove Verilog if you like, but the VHDL should have been there \$\endgroup\$ – CapnJJ Jan 28 at 20:45
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    \$\begingroup\$ Already did, @CapnJJ :) The vhdl is very welcome! \$\endgroup\$ – Marcus Müller Jan 28 at 20:47

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