So this query is related to DC synthesis compiler for digital design.
I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters [name_of_params] only to the top level design or to each entity under it and specify the individual params?
Here's a link to my code snippet.
PS: if it's not clear, let me know; I will upload a screenshot then!