I get confused on how to apply these steady-state analyses when a DC link capacitor is inserted, along with the leakage inductances. I understand volt-sec balance for the magnetization inductance though.
The circuit I am talking about is here please disregard component values as I am just trying to grasp theoretical operation:
For instance, let's say the converter is in the first mode which is when both FET's are on. How do you apply the volt-sec balance to the secondary side? would the KVL for the secondary side look like Vsecondary - Vleak_inductor_secondary - Vmain_inductor - Vout = 0 (please accept the polarities I have assumed)? If so how do you deal with the leakage inductor in the overall equation when determining the input to output voltage relation? Also, it seems that the inductor would ramp up during this stage of when the FETs are on, but at the other stage(s) how does this inductor burn off the energy so it doesn't continually ramp up each cycle? Back through the transformer?
For the DC link capacitor does charge balancing need to be applied? And should I incorporate this capacitor's effect in the charge balance waveform on the output capacitor?
Hopefully, my questions are clear but if they are not please let me know.
Thank you in advance!