I have some trouble understanding a basic concept. Here is my question.

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This is from a document which can be found on the website,


The text accompanying this figure states, “The voltage signal produced by sound modulates the gate voltage of the JFET, labeled VG in Figure 2 causing a change in the current flowing between the drain and source of the JFET (IMIC). An extremely high resistance, RG, may be included to bias the gate of the JFET.”

I have a question regarding the above statement,

  1. Why is the resistance RG needed after all?

If the Voltage produced by the sound changes the current between the Drain and the Source, what is the role of the Resistor? Can't the circuit work without the resistor? I can read from the document it says the Resistor biases the gate of the JFT. I don’t understand what this ‘bias’ means. What does it mean to ‘ bias X/Y”?


What is "bias"

A (DC) Bias is an operating point we set for a device. Choose or set it wrong and the device (the JFET) will not amplify the signal as it is intended to do. Typically an N-type JFET is biased at Vgs = 0 V. See this question. That way the current through the JFET can increase a bit but it can also decrease a bit. That is useful for amplifying AC signals (like sound).

Why is the resistance RG needed after all?

Without Rg the DC voltage at the gate could be undefined. If somehow an electric charge gets trapped on that gate that could lower or raise the DC biasing voltage of the gate. That would then DC-bias the JFET at the wrong gate voltage. Fpor example if the voltage at the gate would become very low, below the pinch off voltage of the JFET, no current would flow through the JFET (it is off) and no signal amplification can take place. That's not useful so we want to avoid that situation.

How could that electric charge end up on the gate?

Since the gate of a JFET isn't really isolated but relying on a reverse biased PN junction there will always be leakage currents which can charge/discharge the gate. See the wikipedia article.

The Rg resistor's task is to keep the gates' DC voltage at 0 V so Vgs = 0 so that the JFET is biased properly and providing the signal gain that it is supposed to deliver.


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