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When designing the layout of a CMOS inverter, we need to use an NWELL to build the PMOS.

Following scalable rules, when desining the masks I have to be sure that if I want to build two NWELLS using the same mask, they have to be separated by, at least, 6 lambda (while two N+ implantation only 3 lambda.)

  • Why do they have to be separated?

  • Can't I build two PMOS in the same NWELL?

  • What happens if they touch each other?

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The DRC rule you are referring to is the separation of two wells at different potentials. DRC has no way of knowing what is the potential of the well (no connectivity information at this level), so if you have two separate NWELLS it will enforce this rule.

If you have two NWELLS at the same potential then you have two choices:

  • Directly abut them, so that these become a single NWELL
  • Separate them by the DRC rule minimum, so that the DRC rule checker does not give you an error and you don't run into further problems (see below)

Do note that on digital circuits, due to switching transients, two separate NWELLS will temporarily develop different potentials during normal operation. As the separation becomes an NPN region, you run the risk of triggering parasitic junctions on the design which can lead to some nasty outcomes.

This is not an issue if the well is a single unit, and it has enough well contacts to handle the potential disparities that develop across it.

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What is an NWELL?

Silicon wafers are generally P-type silicon so suitable for making NMOS transistors. PMOS transistors need to be placed in N-type silicon. To provide this, an NWELL area is made and in it the PMOS are placed.

Normally the NWELL is connected to the positive supply, VDD. That is needed to keep the NWELL area isolated (by a PN junction biased in reverse mode: P-type substrate = VSS, NWELL N-type = VDD).

You can share the same NWELL between as many PMOS as you like as long as these PMOS do not need their NWELL to be connected to a different supply.

For inverters and other logic circuits there generally is only one supply and all NWELLs are connected to that supply. In the layouts of CMOS logic cells I have seen the NWELL areas are shared between many logic cells in order to make the layout smaller. So sharing one NWELL is very common, you can do that as well.

Only when you have a specific reason not to share the NWELLs would you deviate from this. Usually this is the case only for level shifters and some analog circuits.

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