Writing a VHDL Module

I am trying to get through this section of a course: http://hamsterworks.co.nz/mediawiki/index.php/Module_9

I am trying to write the 30 bit counter module (Project 9.1 on the page). I have the counter wrote in a normal .vhd file from the previous sections in that course. Here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Clock_Signals is
Port (  switches : in STD_LOGIC_VECTOR(7 downto 0);
buttons     : in STD_LOGIC_VECTOR(3 downto 0);
LEDs     : out STD_LOGIC_VECTOR(7 downto 0);
clk      : in STD_LOGIC
);
end Clock_Signals;

architecture Behavioral of Clock_Signals is
signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
signal incHighNext : STD_LOGIC := '0';

signal buttonsPrev : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
begin
LEDs <= counter(29 downto 22);

count: process(clk)
begin
if rising_edge(clk) then
-- Allows for a step through
--if (buttons(0) = '1') and (buttonsPrev(0) = '0') then
--counter <= counter+1;
--end if;

counter(29 downto 15) <= counter(29 downto 15)+incHighNext;

if counter(14 downto 0) = "111111111111110" then
incHighNext <= '1';
else
incHighNext <= '0';
end if;

counter(14 downto 0) <= counter(14 downto 0)+1;

-- Update state
buttonsPrev <= buttons;
end if;
end process;

end Behavioral;


But when I make a module, I can't figure out how to translate it over. Here is my current module:

module mymodule(
input [3:0] clk,
input [3:0] enable,
output [3:0] count
);

endmodule

• It looks like you're slipping into Verilog, rather than VHDL. Pay closer attention to the syntax templates provided in the lesson. – Dave Tweed Sep 24 '12 at 1:54
• @DaveTweed That module code is what was generated after created a new Source VHDL Module just like the instructions. I am not sure how I am supposed to translate the code from 6.1 into a module. If I am missing the point then please show me a example. – MLM Sep 24 '12 at 3:03
• Whatever tool you are using, it did not create a new VHDL module. It created a new Verilog module. If you're tool doesn't provide good templates for you, you need to use a different tool, or simply copy templates from a more reliable source. – The Photon Sep 24 '12 at 4:52

I'm pretty sure you accidentally clicked "Verilog Module" instead of "VHDL Module":

The code generated should look something like this:

   COMPONENT mymodule
PORT(
clk    : IN std_logic_vector(3 downto 0);
enable : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;


Delete the accidental Verilog Module and try again paying close attention to which Source Type you choose.