i have a module, written in verilog, that gives me couple of warnings e.g.
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
This is because the bit0 of register "krA" never changes it's state since I'm up counter it by 2. I want to know how can i workaround this warning, maybe if somebody showed me an alternate way of dealing with such a register that will have 1 or more more bits always at a certain logic/state.
Thanks for your time.
link to module : https://pastebin.com/zX4icWu3