# warnings “Xst: 1710 or 1895” in ISE14.7

i have a module, written in verilog, that gives me couple of warnings e.g.

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

This is because the bit0 of register "krA" never changes it's state since I'm up counter it by 2. I want to know how can i workaround this warning, maybe if somebody showed me an alternate way of dealing with such a register that will have 1 or more more bits always at a certain logic/state.

• The warning is telling you that you have a problem with your code. You are trying to create a flip-flop in your circuit and that flip-flop does nothing useful...it can be replaced with a wire connected to ground. Why would you want to "workaround the warning"? – Elliot Alderson Jan 31 '19 at 12:51
• i removed that bit of the register and that warning is cleared now. But when i instantiate this module i get Node unconnected in block "top module" warnings. – jus7ired Jan 31 '19 at 12:57

You can get rid of that warning but you might get another one back.

Start with defining a different reg size reg [4:0] krA; Then adjust all operations to correct for losing the LS bit. Then at the end assign it to krA but setting the LS bit to zero:

reg [4:0] krA;

... // FSM as you had it but half krA:
krA <= Nk * 2;
...
krA <= krA + 1;

assign kr_A = {krA,1'b0};


But now you can have a warning with says something like: "port has static value, This net will be trimmed during the optimization process." (I did not try the code).