i have a module, written in verilog, that gives me couple of warnings e.g.

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

This is because the bit0 of register "krA" never changes it's state since I'm up counter it by 2. I want to know how can i workaround this warning, maybe if somebody showed me an alternate way of dealing with such a register that will have 1 or more more bits always at a certain logic/state.

Thanks for your time.

link to module : https://pastebin.com/zX4icWu3

  • \$\begingroup\$ The warning is telling you that you have a problem with your code. You are trying to create a flip-flop in your circuit and that flip-flop does nothing useful...it can be replaced with a wire connected to ground. Why would you want to "workaround the warning"? \$\endgroup\$ – Elliot Alderson Jan 31 '19 at 12:51
  • \$\begingroup\$ i removed that bit of the register and that warning is cleared now. But when i instantiate this module i get Node unconnected in block "top module" warnings. \$\endgroup\$ – jus7ired Jan 31 '19 at 12:57

You can get rid of that warning but you might get another one back.

Start with defining a different reg size reg [4:0] krA; Then adjust all operations to correct for losing the LS bit. Then at the end assign it to krA but setting the LS bit to zero:

reg [4:0] krA;

... // FSM as you had it but half krA:
krA <= Nk * 2;
krA <= krA + 1;

assign kr_A = {krA,1'b0};

But now you can have a warning with says something like: "port has static value, This net will be trimmed during the optimization process." (I did not try the code).

Just a general remark about your code:

You use ports without reg. Then you define local regs with nearly the same name and at the end you assign them to the port.
That is confusing and superfluous. I prefer the same variable throughout like your did with exor1 and exor2. The fact that you use a mixture of the two is even more confusing to me.

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  • \$\begingroup\$ i just have my own way of naming signals. And as you might have known this is a part of another module and it needs to access block rams as well, i was experiencing some delays since im working in one seq always block(top module) so thats why i was doing these reg to net assigns. \$\endgroup\$ – jus7ired Jan 31 '19 at 10:54
  • \$\begingroup\$ btw i have thought of the same thing of concatinating. \$\endgroup\$ – jus7ired Jan 31 '19 at 10:56

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