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So I have come across this code and when I synthesize it I was surprised that there is no latch.

library ieee;
use ieee.std_logic_1164.all;

entity practising is
port(
    a,b,c: in std_logic;
    z: out std_logic
);
end practising;

architecture behavioural of practising is
signal y: std_logic;
begin

test: process(a, b, c)
begin
    y <= a nand b;
    z <= c or y;

end process;

end architecture behavioural;

I thought it will create a latch as I defined y as a signal so its value will change at the end of the process, therefore, the output Z will keep its value until the process is instantiated again, so there must be a latch to store the value of Z. However, when I synthesized the code there was no latch present. enter image description here

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  • \$\begingroup\$ without knowing what the purpose of the module is, why are we making assumptions on whether it should contain a latch or not? Especially, it's called "practising", which sounds a lot like it was a student practice result, and thus has a high likelihood of actually not being correct. \$\endgroup\$ – Marcus Müller Jan 31 at 17:22
  • \$\begingroup\$ Why should be latch there? Isn't this schematic clearly implementing what is written? signal is a wire, and does not imply anything about being latched. It needs not to be "saved" over iterations as it is always assigned within the process. \$\endgroup\$ – Eugene Sh. Jan 31 at 17:23
  • \$\begingroup\$ As long as A,B and C aren't changing, why do you think Z would change? \$\endgroup\$ – mike65535 Jan 31 at 17:26
  • \$\begingroup\$ You have designed combinational block; if you would put riding_edge into conditions then it would be the latch: nandland.com/vhdl/tutorials/tutorial-process-part2.html \$\endgroup\$ – Anonymous Jan 31 at 17:30
  • 2
    \$\begingroup\$ @Anonymous: you can make a latch without using any edge conditions using an if : if A then B <= C; end if; You get registers (not latches) if you use rising_edge \$\endgroup\$ – Oldfart Jan 31 at 17:40
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Synthesis ignores sensitivity lists and assumes they are correctly and fully written.

Your code with all four signals in the sensitivity list does not describe a latch (since an update on y would force an update on z by rerunning the process), so your code does not describe a latch.

Most synthesis tools will generate a warning in a log somewhere that mentions it assumes as full sensitivity list.

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  • \$\begingroup\$ Pedant mode - synthesis doesn't "assume [sensitivity lists] are correctly and fully written" - it does what you said first, and ignores them :) \$\endgroup\$ – Martin Thompson Feb 11 at 14:29
  • \$\begingroup\$ However, a synthesis simulation mismatch warning comes I guess in Xilinx ISE \$\endgroup\$ – Mitu Raj Mar 19 at 18:29

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