# Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch.

library ieee;
use ieee.std_logic_1164.all;

entity practising is
port(
a,b,c: in std_logic;
z: out std_logic
);
end practising;

architecture behavioural of practising is
signal y: std_logic;
begin

test: process(a, b, c)
begin
y <= a nand b;
z <= c or y;

end process;

end architecture behavioural;


I thought it will create a latch as I defined y as a signal so its value will change at the end of the process, therefore, the output Z will keep its value until the process is instantiated again, so there must be a latch to store the value of Z. However, when I synthesized the code there was no latch present.

• without knowing what the purpose of the module is, why are we making assumptions on whether it should contain a latch or not? Especially, it's called "practising", which sounds a lot like it was a student practice result, and thus has a high likelihood of actually not being correct. – Marcus Müller Jan 31 at 17:22
• Why should be latch there? Isn't this schematic clearly implementing what is written? signal is a wire, and does not imply anything about being latched. It needs not to be "saved" over iterations as it is always assigned within the process. – Eugene Sh. Jan 31 at 17:23
• As long as A,B and C aren't changing, why do you think Z would change? – mike65535 Jan 31 at 17:26
• You have designed combinational block; if you would put riding_edge into conditions then it would be the latch: nandland.com/vhdl/tutorials/tutorial-process-part2.html – Anonymous Jan 31 at 17:30
• @Anonymous: you can make a latch without using any edge conditions using an if : if A then B <= C; end if; You get registers (not latches) if you use rising_edge – Oldfart Jan 31 at 17:40