# Simple NMOS simulation error. High voltage drop across the nmos when trying to make a MOSFET switch

I have this simple NMOS configuration in ltSpice. I would imagine that when V2 (Vg) goes high, Vds would go close to zero. But this simulation suggests that there is a very high voltage drop across the nmos, which is strange to me. What is my error in this simulation? I want to have the nmos act as a "short", or switch when Vgs>some Vth.

(Vn002) is the node just below the 1k resistor

• What's the Vgs(th) of your transistor? For the default in LTSpice it is very likely higher than the 3.5 V you applied. Try using a transistor model with a known low Vgs(th), or applying maybe 10 V with the default model. – The Photon Feb 1 '19 at 6:01

You should not rely on the default settings for the MOS, since those settings are for IC design, which means voltages of tens of volts are unlikely to be sustained. If you open up the manual and go to LTspice > Circuit Elements > M. you'll see that the default values are Vt0=0, gamma=0, Rd=0, ..., to name a few.
If you want to test a specific model, or subcircuit, you should use that .model card, or .subckt definition appropiately, otherwise all you'll get is GIGO (garbage-in, garbage-out).
Also, you're applying a voltage source directly at the gate of the MOS, and voltage sources have internal resistance (machine) zero, unless you specifically add an external resistance, or set Rser=<...> in the voltage source. It's a zero resistance source driving a capacitance, what could go wrong I wonder?