So, I actually have come to realize that the idea of "yeah I want a mux here and then an AND gate here" is faulty if you're using an FPGA. You can never ever assume that just because you wrote it one way means that it will actually be implemented the exact way you say. It will, however, have the same truth table when you boil it down. So, you've got to think of things one level above muxes and gates (this is one reason why the register-transfer level (RTL) is so popular for design with FPGAs).
You may already know this and I'm just being thorough by bringing this up, but here's the problem: When you ask an FPGA to do something, it will use something the following to actually implement it (Example from a 7-Series Xilinx FPGA from UG474):
When you say "I want a mux", its just going to implement that same logic circuit using the LUT6 (the four boxes farthest to the left) which basically a 64x2 RAM programmed with the truth table for your logic. If you want a latch or register, it will use a flip flop in that same logic block configured in the way you specify (found on the right).
So all we've got is a bunch of 6-input, 2-output lookup tables combined with some flip flops to implement whatever you'd like. Because of this fact, it is usually not the best idea to think of things in terms of gates since that might lead you to make some false assumptions. For example, you might assume that the following VHDL would be glitch free (i.e.
theOutput doesn't change) if
myAsyncSignal was low while
myGatingSignal went high:
theOutput <= myAsyncSignal and myGatingSignal;
In reality, this would be implemented in that LUT6 using two of the inputs and one of the outputs. There's no guarantee of glitch-free-ness there (even if it shows up as glitch free in simulation). This is why when designing for FPGAs you often need to register your outputs in a flip flop and have no intervening (output-forming) logic if you're going to next check for an edge on that signal without using a clock.
Also, even putting a schematic in ISE or Vivado won't actually cause that exact schematic to be implemented. That schematic will go through the "implementation" step and be forced into LUTs just like logic you would have made in HDL.
If you really really care that you use a MUX and logic gates for the implementation (as you might with a clocking circuit), then you need to start designing an ASIC, or build it out of actual logic chips, or prototype it on a breadboard. Or maybe consult your device's many manuals to see if there's some hard IP built into the FPGA that might fit the bill. Some CPLDs are also suited to doing this kind of thing since they are sometimes implemented as a bunch of AND-OR logic with an optional flip flop. But, if all you want to do is implement some process and you have a good truth table description of it, then an FPGA is a great tool to use. Turns out that many, if not most, applications fit into that idea and that's what makes FPGAs popular.