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I was studying a Texas Instrument reference board and would like to understand some topologies and PCB routing techniques. The project is a 230-V, 3.5-kW PFC with >98% Efficiency.

Here's the complete project page where you can download the CAD files: TIDA-00779 CAD Files.

I would like to start asking what are the reasons for using these marks on the bottom solder layer?

Marks on solder layer (2D view) Marks on solder layer (3D view)

If anyone observes another interesting feature or technique used in the design of this board, please share with us.

Thank you.

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    \$\begingroup\$ Sometimes you see high-current traces with the soldermask taken off because adding solder reduces the trace resistance by making it effectively thicker (even though solder has a much lower conductivity than copper, it still has some effect). \$\endgroup\$ – Hearth Feb 2 at 0:41
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    \$\begingroup\$ looks like a heatsink to me... \$\endgroup\$ – dandavis Feb 2 at 0:41
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    \$\begingroup\$ Notice they are on top of fat traces, perhaps for more copper pour as well as heat dissipation. \$\endgroup\$ – Sparky256 Feb 2 at 3:19
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    \$\begingroup\$ The thermal gradients maybe increase turbulent convection which improves the usual 80’C/W per sq.in. 1oz copper. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 2 at 3:30
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It is common practice to leave areas relieved from solder mask on power traces in order to increase the surface exposed to the air, and therefore dissipate the excess heat. This allows to increase the upper limit of current that can flow through a section of track, especially useful if there is a lack of space.

This method is not recommended to be used in case that the board is exposed to dirty air such as oil+dust, where the dirt can accumulate on the board and create low resistance paths between tracks. Otherwise from that it is a good method for dissipating the excess heat.

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