For the amplification of piezoelectric sensor signals I am currently building a charge amplifier with a low noise JFET frontend utilizing an NXP BF862. The amplifier design is based on application notes from Linear Technology/Analog Devices (Design Note 254 and Design Note 308). My schematics and PCB layout are as follows:
My problem is that the measured noise is too high. For a capacitive test source (just a capacitor) of 264 pF I need an output referred noise floor below 100 nV/rtHz for frequencies between 800 Hz and 900 Hz. According to my LTspice simulation this should be achievable, the overall noise floor at 850 Hz is 52 nV/rtHz:
However, after producing the PCB several times with different layouts and measuring the noise floor at the amplifier output the result was always the same: Approx. 250 nV/rtHz at 850 Hz. Referred to the input that means approx. 9.5 nV/rtHz, which I think is much too high. I am doing these measurements in a faraday cage with a SR785 FFT analyzer whose input noise is well below 10 nV/rtHz. I changed the BF862 several times and I also increased the feedback resistance to up to 50 GOhm. But the noise floor always kept exactly the same. The amplifier was powered via two lead acid batteries. So, the simulated noise (52 nV/rtHz) is roughly a factor of five lower.
Does anybody have an idea what the problem could be, i.e. where the noise is coming from? Is it possible that the simulation is wrong? Or could it be that one of my components is not behaving like expected? For example I thought that maybe the feedback resistance (or the source/drain resistances) adds some kind of additional 1/f noise? I also checked all the DC operating points, but they are correct, i.e. like in the simulation. What would you try next?
Thank you very much for your help!