For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx connected with TI's DAC38RF80EVM through an FMC connector and are hoping to run them off the same device clock. As such and to my understanding, we should need a clock that is at least two times the max output frequency (Nyquist criterion), so a 4 GHz or greater device clock should be used to run both devices off of.

That said, I was wondering if this is possible on our current selected FPGA? I know that GTH transcievers that pump the data through the FMC can work at data rates in the 16 Gbps range, but the clocks on the FPGA that can run them appear limited. Our DAC does feed the Clock and SysRef signals back through the FMC connector (see attached diagram). Could that be used by the FPGA? Or for some reason, do we not need a clock that fast for this application? Or is there anything else we may be missing?

I know this question is a bit of a doozy, but any help that can be provided would be greatly appreciated.

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  • \$\begingroup\$ You should write the VHDL or Verilog code that you need and compile it for your target FPGA. The tools will give you a timing analysis that will answer your question. \$\endgroup\$ – Elliot Alderson Feb 4 at 16:31

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