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  1. I am working on a circuit that needs reverse current protection. Back to back mosfet configuration has been suggested by many people, and it seems to make sense at the beginning. But after I built my PCB, after fully charged my capacitor, and then turned off the power supply, the current flowed right back to the power supply.
  2. Let me explain my circuit a little bit. I need to charge C1 and use it to run a pulsed (D=10%) circuit that requires every large current. I have a separate circuit that controls the max current to charge the capacitor, so that I do not need to worry about charging current for this circuit. During charging, my intention is to using R4 and R10 to keep Q1 and Q2 on when power supply is turned on; R2 and R8 sets up a node voltage that is always less than the gate voltage at Q1 and Q2 unless Q6 is turned off. When the power supply is on, R7 and R11 keep Q6 on. D2 blocks the current flowing to C1. Everything works on charging my capacitor. During discharging, when Power supply is turned off, R7 and R11 has no current flowing through and Q6 is off, and the gate voltage on Q1 and Q2 is pulled up to something like +49.5V, and Q1 and Q2 shuts off. Here is the problem, Q1 and Q2 were never turned off. My theory is that any parasitic capacitance or slow power supply turn off action that can keep Q6 on for a very small mount of time, Q1 and Q2 will stay on, and current starts to flow back, and then most of the voltage on C1 appears at Vin and keeps Q6 for longer period of time. It creates a positive feedback loop and keep Q1 and Q2 on.
  3. I have done simulation and confirmed that the Q1 and Q2 are on during discharging(Discharging circuit not shown here).
  4. I would love to have some feedback from someone who has gotten this circuit working before or someone who knows what's keeping Q1 and Q2 on when the power supply is turned off.
  5. If you have different ideas on how to block the reverse current, I would love to hear them too. Using diode is not an option because forward current is too high, diode gets too big and consumes a lot of power.

Thanks! Schmetic

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  • \$\begingroup\$ Have you tried giving Q6's gate some other path to discharge? Or just reducing the magnitude of the resistors in that voltage divider might be enough. \$\endgroup\$ – Hearth Feb 4 at 20:28
  • \$\begingroup\$ Tried to simulate R7=390 and R11 = 100. Still cannot keep Q6 off. Even if it did at this resistance, it's impractical because +50V/(R7+R11) allows too large of a current to be wasted during normal operation. I did manually pulled Q6 gate low in the simulation, Q1 and Q2 remained off after I let go Q6 gate manual control. But I would like this control signal to be derived from Vin. When Vin is not present, control signal turns off Q6. The only way I got it to work was to put a resistor in the path and detect the reverse current. \$\endgroup\$ – hong pan Feb 5 at 19:07
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You are absolutely correct - the circuit will remain on until Q6-gate goes below its gate threshold voltage of one volt. Q2 will conduct through it body diode, so Q1-source has to make it down to a voltage below its gate threshold voltage before it turns off and the voltage on C1 will appear on at Vin until this occurs. In addition to lowering the impedance to speed up switching times as @Hearth suggests, you will have to actively drive "off" circuit after comparing Vin and Vout.

You might look into an ideal diode controller such as the LT4320/4321.

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  • \$\begingroup\$ It seemed very obvious that my control signal to Q6 is flawed after I built and tested the circuit. And I did a lot more research on the internet afterwards. No one seems to use PMOS for reverse current protection on the high side. It is always NMOS with driver IC. NMOS might have lower Rds,on, but I think the reason is because PMOS is too easy to turn on and stay on on the high side, whereas NMOS needs gate voltage is higher than input voltage to turn on. \$\endgroup\$ – hong pan Feb 5 at 19:16
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You cannot expect Q1 & Q2 to turn off when all of the bias paths to their gates pull them towards ground (I.e., |Vgs|>0 always).

You have to explicitly pull up the gates to their source voltage to turn them off. Although it is a useful approximation, it is a misconception that |Vgs|<|Vt| turns a FET completely off, its current will be relatively small, but it actually enters what is known as the subthreshold regime. You are applying around 0.6V, depending on the diodes you are using.

The “leakage” current in this regime might be more than enough to justify what you are seeing.

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  • \$\begingroup\$ I did a simulation where I replaced D2 with a wire. Q1 and Q2 still got turned on. I did another simulation where I pulled Q6 gate low "manually". It turned off Q1 and Q2 and no more reverse current flowed as soon as I turned off Q6. Even after let go of the Q6 gate control, Q1 and Q2 remained off. I do not think D2 is the problem here. But thanks for your idea. \$\endgroup\$ – hong pan Feb 5 at 18:55
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Here is the problem, Q1 and Q2 were never turned off.

Correct. Back-to-back FETs can be used to isolate two supplies, but only if the control signal is separate. You are trying to control them with the same voltage that they are switching, which won't work because when the FETs are on Vin is shorted to C1 so when you turn off the power supply Vin still has the voltage of C1 on it - therefore preventing Q6 from turning off.

To block reverse current using only the input and output nodes you need a diode, or a circuit that simulates a diode (ie. measures the voltage drop or current flow from one side to the other, and derives a control signal from its polarity).

Using diode is not an option because forward current is too high, diode gets too big and consumes a lot of power.

Your proposed circuit uses two IRF5210 MOSFETs which have on-resistance of ~0.06Ω and drop ~0.6V each at 10A, for a total voltage drop of 1.2V and power loss of ~12W. A Schottky diode like the VB40100G (40A, 100V) would have lower voltage drop and power loss, and since no other components are required it would take up less board space. Also, unlike a FET the diode's voltage drop reduces as it gets hotter, making it more efficient. The only downside is increased leakage current (~5mA at 125°C and 50V).

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  • \$\begingroup\$ You're exactly right about that the way my control signal to Q6 is flawed. But I really wanted to a control signal to turn off Q1 and Q2 coming from detecting the presence of Vin. There is a separate current limiting circuit using one of the PMOS that is not shown because I did not want to add confusion. At a slow ramping duration of 200ms, the IRF5210 was barely staying in the safe operating area because initial voltage drop is so high when current limit is at 3A. I am really only using one PMOS as reverse current block. If you do that calculate, using Mosfet has more advantage. \$\endgroup\$ – hong pan Feb 5 at 19:32

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