One time I built a 3 phase motor driver, which works quite well in the original configuration. Recently, I changed the physical layout to this rectangular form factor, and now it has quite large switching transients accompanying the rising and falling edges of each switch node. The transients go so high that if I run at full 60V, they kill the board dc/dc converter!

Here is the old form factor board which works quite well and has driven a BLDC motor at 4kW from 48V (there is a logic board which goes on top and capacitor board which goes behind): enter image description here

Here is the new board which has very large switching transients: enter image description here

Here is the rising edge: enter image description here

Here is the falling edge: enter image description here

Attempted solutions: I tried changing the gate resistance. The circular board has gate resistors of 12 Ohms and no resistor on the bootstrap line. The rectangular board has 40 Ohm gate resistors, 4.7 Ohm bootstrap, and much longer deadtime, but the transients are totally un-affected. Snubbers don't seem to do anything. Ringing is ~17MHz. Adding or removing ceramic caps doesn't do anything noticable, nor do schottky diodes.

What did I change between the two layouts that causes this type of ringing? The only real difference I can point to is the B2B headers. Board power, and the fet driver signals come out the right, along with the bootstrap lines. Board ground is on the left, along with the analog sense signals. I'm hesitant to spin another board, buy new parts, spend 6 hours assembling and all that without some clue as to what I did wrong on this revision :( Does anyone have an idea?


I am going to re-do the layout of this board according to two principles: 1) put a ground plane under all of the control lines 2) keep the highgate+bootstrap, and lowgate+return as close together as possible. I will then share my results (and probably change careers if it doesn't work).

Here is the layout plan for the switching board. There is only one B2B connector. It gives 4.3mm between boards. The paths of the control lines are in blue, and they travel in between the drain and source connections, where there will be heat vias coming down. I have extended ground on the inner plane it such that the HF signals will always be over the ground plane, and will do the same on the bottom layer, so that the signals are sandwiched by ground planes. I would like to not have gate-resistor-per-fet, but because of the situation I am in a mood to follow all best-practices. enter image description here I appreciate any comments if you have them.

  • \$\begingroup\$ Did you also measure the old board? \$\endgroup\$
    – Jeroen3
    Feb 5, 2019 at 6:42
  • \$\begingroup\$ The circular board has switching transients as well, but they are not significant. It's around 500-1300mV depending on load. I would be very happy if I could learn what I did to make the square board so much worse! \$\endgroup\$
    – NickW
    Feb 5, 2019 at 6:49
  • \$\begingroup\$ show ALL the PCB layers, and show the schematic. And explain the waveforms. 100 amps switching in 1uS, thru 4" (100nanoH) of wire (no nearby RTN wire or plane), produces V = L * dI/dT = 0.1uH * 100A/1u = 10 volts. And 100 amps switching in 100 nanoSeconds thru 4" wire produces 100 volts of inductive kick. \$\endgroup\$ Feb 5, 2019 at 9:45
  • \$\begingroup\$ Now lets discuss inductive coupling. If you have a wire carrying 100 amps, the current switching in 100 nanoseconds (or 1 GigaAmp/second), and that wire runs 1cm away from a 1cm by 1cm loop on your control board, you will have Vinduce = 2e-7 * 1cm * 1cm/1cm * 1e+9 = 2 volts induced into your control board. Can your control PCB tolerate 2 volts induced onto EVERY TRACE of the circuit? \$\endgroup\$ Feb 5, 2019 at 9:48
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    \$\begingroup\$ The Alum housing gap geometry is essential to controlling impedance and orthogonal paths are critical, can you do a math plot of V/I for input and output under different loads for the round board, the square one in air is NG \$\endgroup\$ Feb 5, 2019 at 13:59

1 Answer 1


wire to loop coupling model and math


simulate this circuit – Schematic created using CircuitLab

NOTE: this formula [ Vinduce = 2-7 * (Area/Distance) * dI/dT] is conservative; the exact math uses a natural_log to include effects of the two sides of the loop that are at 2 different distances (here 1cm for the near side, and 2cm for the far side).

WARNING: if you are concerned about this level of Vinduce accuracy, then you have a dangerous system design (IMHO) and need to use serious mitigation methods.

  • \$\begingroup\$ Couldn’t have said it any better than this. The OP needs to control impedances of power switching and crosstalk \$\endgroup\$ Feb 5, 2019 at 13:46
  • \$\begingroup\$ Thank you! The rectangular board is not yet switching 100A. The scope shots are the gate waveforms (high and low) and power input with the motor running at 300mA. This problem must be something else. The circular board works very well at 100A (for 30 seconds). It does not exibit any issues with any sort of ringing or inductively coupled noise or crosstalk. There is something which I did differently between the two boards. I will post the layout. Is it common to set gate drive trace width and space as a stripline? \$\endgroup\$
    – NickW
    Feb 5, 2019 at 20:53
  • \$\begingroup\$ The point of Sunnyskyguy is the NEED to control the return paths of all your fast high-current edges. That means have GROUND plane (or the aluminum housing) adjacent to all your fast high-current edges. \$\endgroup\$ Feb 6, 2019 at 3:35
  • \$\begingroup\$ Thank you ASsrf, I think I see what you mean. I did not control the return path for the gates, nor did I control the return for the bootstrap. Next rev, I will follow these rules: 1) put a ground plane under all of the control lines 2) keep the highgate+bootstrap, and lowgate+return close together. \$\endgroup\$
    – NickW
    Feb 6, 2019 at 4:07
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    \$\begingroup\$ NickW Please share your results. This is quite a challenge you are handling, and very interesting. \$\endgroup\$ Feb 6, 2019 at 11:36

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