# Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same frequency magnitude? Why make the PLL working at 1:16 frequency? Any benefit?

There are many subtleties to PLL design, in addition to whether things will work fast enough.

Obviously, the phase detector (PSD) has to work fast enough. The 3-state PSD in analog's answer requires a time delay in the feedback path. Its linearity improves as the delay increases, so there is a speed tradeoff.

The rest of my answer is going to concentrate on the often overlooked effects of PSD saturation.

A typical phase detector will saturate at a small phase offset. The 3-state saturates at +/- 1 cycle, though other types will often not go that far, and some can be built to go further. This saturation has some interesting consequences.

Let's say the PLL is designed to recover the carrier from an FM modulated signal. If the phase deviation of the signal exceeds the PSD saturation range, then the loop will go non-linear, which could cause problems depending on what the recovered average frequency signal was going to be used for. Putting a /16 divider in front of the PSD effectively moves its saturation level to +/- 16 cycles, so it can tolerate a much larger phase deviation before going non-linear.

Let's say the PLL is designed to rapidly acquire lock when presented with a new signal. Let's assume the PLL requires some particular bandwidth, for noise performance when locked, which means a particular gain round the loop. When far from lock, PSD saturation will limit how fast the loop can be driven towards lock. If, without changing the total gain round the loop, we divide the frequencies by 16 and multiply the analog gain after the PSD by 16, then the total loop gain and so loop dynamics when in lock remains unaltered (can remain essentially unaltered, see comment discussion below). However, the saturated PSD will now drive towards the lock point 16 times faster when out of lock.

As divided PSD like this will result in an increased contribution of PSD noise in the locked bandwidth. This may or may not be relevant in any particular situation. Different PLL applications will have different specifications, and so different tolerance of PSD noise. There is no one-size-fits-all answer.

• Neil_UK I like the details of your answer. However, division drops the control bandwidth by (16:1? 4:1) and hurts the frequency response, losing modulation information; perhaps instantaneously changing from 16:1 to 1:1, once locked, will provide the benefit of both divisors. Also, I don't think the "linearity" will continue to improve, once the delay is long enough to let both the FlipFlops reach steady internal node voltages and let the Charge Pump switches reach steady internal currents. – analogsystemsrf Feb 6 '19 at 11:14
• @analogsystemsrf Division increases the latency of the loop, so may result in a need to reduce the bandwidth for stability. If latency is small, you get the same bandwidth loop if you keep compensate with gain to keep the loop gain constant. My answer was simplified to ignore latency. I sort of agree with you on 3 state linearity. I meant it gets worse as the time reduces, though I agree that the rate it gets better as the time increases becomes asymptotic. I've used 4 state PSDs where no amount of delay increase in 3 state made them linear enough (3 and higher accumulator all digital fracN) – Neil_UK Feb 6 '19 at 12:24
• Neil_UK Thanks for the details. Never needed to use the higher-state PFDs. My focus was on predicting the various jitter floors, so we could achieve high-slew-rates (by burning power) only where needed, and have the designs be first-pass-successes. – analogsystemsrf Feb 7 '19 at 12:20

If the FlipFlops are working near max clock rate, the internal silicon nodes will not be in steady-state, and the deterministic jitter will be unpleasant to handle. [corrected math error Feb 8, 2019. 63uV should be 6.3uV]

Additionally, some small delay is used in the feedback (reset-the-Flops) path, to ensure the Q outputs have time to produce FULL AMPLITUDE output levels. Like this

simulate this circuit – Schematic created using CircuitLab

How much jitter will the RC delay insert? (assuming the VDD rail is quiet; typical logic has ZERO dB or perhaps 6dB Power Supply Rejection; a risk of slow edges from the RC delay is the increased vulnerability to Rail trash, contributing to deterministic 60/120/1MHz_switch_reg jitter).

The noise voltage of a capacitor is sqrt(K*T/C), and is 20 microVolts RMS for 10 pF(easy to remember). For 100pF, this increases 3.16x to 63 microVolts. <<<==== WRONG. This decreases, to 6.3 microVolts.

To compute the added jitter of this noisy node (which is the input to that NAND2 gate), we need the SlewRate of the RC signal at VDD/2, assuming the gates are biased for VDD/2 switching as linear amplifiers. The initial SlewRate will produce exactly RC=TAU delay; with 5 volt rails and with 100 nanoSec TAU, the edge rate will be 5 volts in 100 nanoseconds or 1v/20nS or 50 milliVolts/nanosecond. If we waited to trip (cross the threshold) to 63% (we expect 50% trip), our slewrate will be exactly 1/e (1/2.718) slower or 37% of initial; since we are (assumed) crossing the (linear-internal-gate amplifier) at 50%, lets avoid the math and simply assume a 2:1 lower slewrate instead of 2.718 slower; this makes the slewrate become 50 mV/nS times 50% or 25 millivolt / nanosecond.

Now we can compute the jitter added by this RC delay.

Tj = Vnoise / SlewRate

TimeJitter = Total Integrated Noise RMS Voltage/ SlewRate at Zero Crossing

Tj= 6.3 microVolts / (25 milliVolts / nanosecond)

Tj = 6.3 microVolts / (25,000 microVolts / nanosecond)

Tj = 6.3/25000 * microVolts/microVolts * 1/(1/nanosecond)

Tj = 1/4,000 nanosecond = 0.25 picoSeconds time jitter, total integrated

The delay bandwidth (100 nanosecond) is 1.6MHz; round up to 4MHz, because of the PI/2 factor (2.5MHz if brick-wall rolloff model) and to make the next math easy.

If we have 4MHz bandwidth, the noise density is 0.25pS/sqrt(4,000,000) or 0.25pS/2,000 = ~~ 0.1 femtosecond/rootHertz RMS additive random noise, up to about 1.6MHz and then rolling off. In other words, 100 attoSeconds/rtHz.

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Notice the SlewRate is key to setting how the thermal Noise is converted into edge jitter. With the RC delay, we have a predictable SlewEate. What is the SlewRate INSIDE those logic gates? Consider this

simulate this circuit

• If I would use 74AS74 (9ns max) and 3x serie 74AS00 (4.5ns*3=13.5ns) to lock a frequency of 705KHz (11.2Mhz/16), how should be a "safe" RC delay to avoid dead zone? – Gianluca G Feb 6 '19 at 14:21
• As long as the charge pump can completely switch in 9+13.5 = 22.5 nanoSeconds, you may not need any delay. But provide excellent VDD bypassing on the PFD rails and on the ChargePump rails. Avoid ripple. Learn to dampen the VDD. – analogsystemsrf Feb 7 '19 at 3:08
• In the circuit (which I'm going to replicate: members.chello.nl/~m.heijligers/DAChtml/dig_r2c.pdf ) I don't have any charge pump stage: I just have a LPF (U17) after the PFD. The original scheme doesn't have any delay network after the 74HC00 (U15) nor has any serie gates to delay the signal applied to the latches (74HC74 U14-U13) like you and most of the PLL designs suggest. Now I'm going to improve it by replacing with much faster 74AS logics. I'm wondering now if I need the delay network in that scheme in order to improve it and, if so, how many ns to delay I would need. Thanks – Gianluca G Feb 7 '19 at 5:56
• If you are going for lower phase noise, I'd be careful using TTL logic. As the internal common-anode junction (where the 2 or 3 or 4 input emitters have their bases shared) rises, that node is SLOW and has high-value resistor pullup (LSTTL has 40Kohm pullup; I don't know about AS internal pullups). Pulldown may be less jitter; I dunno. But Tj = Vnoise/SlewRate still defines the jitter contribution, whether slow-pullup or fast-pulldown; here the jitter will be seriously DIFFERENT, depending upon the edge polarity. Regarding delays --- use 10 nanoSeconds, with a trimmer capacitor to experiment. – analogsystemsrf Feb 7 '19 at 20:28

Why make the PLL working at 1:16 frequency

quite possibly simply because the phase detector simply doesn't work reliably enough at the VCO frequency itself.

• I thought the same. In fact I put in the graph the chips technology making phase detector: But 74HC74 should work at 25MHz, hence should be fast enough for the clock signal (11.2MHz) – Gianluca G Feb 5 '19 at 21:03
• @GianlucaG, TI's 74HC74 has a propagation delay of 15 ns. If you use it at 10 MHz, the propagation delay is 15% of the period. That could cause a pretty big offset error in the control signal. – The Photon Feb 5 '19 at 21:28