I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same frequency magnitude? Why make the PLL working at 1:16 frequency? Any benefit?
There are many subtleties to PLL design, in addition to whether things will work fast enough.
Obviously, the phase detector (PSD) has to work fast enough. The 3-state PSD in analog's answer requires a time delay in the feedback path. Its linearity improves as the delay increases, so there is a speed tradeoff.
The rest of my answer is going to concentrate on the often overlooked effects of PSD saturation.
A typical phase detector will saturate at a small phase offset. The 3-state saturates at +/- 1 cycle, though other types will often not go that far, and some can be built to go further. This saturation has some interesting consequences.
Let's say the PLL is designed to recover the carrier from an FM modulated signal. If the phase deviation of the signal exceeds the PSD saturation range, then the loop will go non-linear, which could cause problems depending on what the recovered average frequency signal was going to be used for. Putting a /16 divider in front of the PSD effectively moves its saturation level to +/- 16 cycles, so it can tolerate a much larger phase deviation before going non-linear.
Let's say the PLL is designed to rapidly acquire lock when presented with a new signal. Let's assume the PLL requires some particular bandwidth, for noise performance when locked, which means a particular gain round the loop. When far from lock, PSD saturation will limit how fast the loop can be driven towards lock. If, without changing the total gain round the loop, we divide the frequencies by 16 and multiply the analog gain after the PSD by 16, then the total loop gain and so loop dynamics when in lock remains unaltered (can remain essentially unaltered, see comment discussion below). However, the saturated PSD will now drive towards the lock point 16 times faster when out of lock.
As divided PSD like this will result in an increased contribution of PSD noise in the locked bandwidth. This may or may not be relevant in any particular situation. Different PLL applications will have different specifications, and so different tolerance of PSD noise. There is no one-size-fits-all answer.
If the FlipFlops are working near max clock rate, the internal silicon nodes will not be in steady-state, and the deterministic jitter will be unpleasant to handle. [corrected math error Feb 8, 2019. 63uV should be 6.3uV]
Additionally, some small delay is used in the feedback (reset-the-Flops) path, to ensure the Q outputs have time to produce FULL AMPLITUDE output levels. Like this
How much jitter will the RC delay insert? (assuming the VDD rail is quiet; typical logic has ZERO dB or perhaps 6dB Power Supply Rejection; a risk of slow edges from the RC delay is the increased vulnerability to Rail trash, contributing to deterministic 60/120/1MHz_switch_reg jitter).
The noise voltage of a capacitor is sqrt(K*T/C), and is 20 microVolts RMS for 10 pF(easy to remember). For 100pF, this increases 3.16x to 63 microVolts. <<<==== WRONG. This decreases, to 6.3 microVolts.
To compute the added jitter of this noisy node (which is the input to that NAND2 gate), we need the SlewRate of the RC signal at VDD/2, assuming the gates are biased for VDD/2 switching as linear amplifiers. The initial SlewRate will produce exactly RC=TAU delay; with 5 volt rails and with 100 nanoSec TAU, the edge rate will be 5 volts in 100 nanoseconds or 1v/20nS or 50 milliVolts/nanosecond. If we waited to trip (cross the threshold) to 63% (we expect 50% trip), our slewrate will be exactly 1/e (1/2.718) slower or 37% of initial; since we are (assumed) crossing the (linear-internal-gate amplifier) at 50%, lets avoid the math and simply assume a 2:1 lower slewrate instead of 2.718 slower; this makes the slewrate become 50 mV/nS times 50% or 25 millivolt / nanosecond.
Now we can compute the jitter added by this RC delay.
Tj = Vnoise / SlewRate
TimeJitter = Total Integrated Noise RMS Voltage/ SlewRate at Zero Crossing
Tj= 6.3 microVolts / (25 milliVolts / nanosecond)
Tj = 6.3 microVolts / (25,000 microVolts / nanosecond)
Tj = 6.3/25000 * microVolts/microVolts * 1/(1/nanosecond)
Tj = 1/4,000 nanosecond = 0.25 picoSeconds time jitter, total integrated
The delay bandwidth (100 nanosecond) is 1.6MHz; round up to 4MHz, because of the PI/2 factor (2.5MHz if brick-wall rolloff model) and to make the next math easy.
If we have 4MHz bandwidth, the noise density is 0.25pS/sqrt(4,000,000) or 0.25pS/2,000 = ~~ 0.1 femtosecond/rootHertz RMS additive random noise, up to about 1.6MHz and then rolling off. In other words, 100 attoSeconds/rtHz.
Notice the SlewRate is key to setting how the thermal Noise is converted into edge jitter. With the RC delay, we have a predictable SlewEate. What is the SlewRate INSIDE those logic gates? Consider this
Why make the PLL working at 1:16 frequency
quite possibly simply because the phase detector simply doesn't work reliably enough at the VCO frequency itself.