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For minimizing SMPS ripple and especially noise, I’m trying to make a small interface which is a post regulator cascaded after an LC filter. I have come across some papers related to this topic and the idea is to establish good noise rejection by using a low drop out LDO regulator for frequencies lower than like 100 kHz and for higher frequencies by using an LC filter. At this video it also gives a very nice example at around 2:56.

The topology can be seen in the circuit I have drawn in LTspice. Here is my circuit in question(the one inside the dashed box is the filter):

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The circuit is set for 120mA load with 12V regulator output to a 15V input.

Now my biggest problem in simulation was that since I don't know the DC output resistance R3 of an SMPS and it can be different for any different SMPS. So for the worst case I took it as 0.02 Ohm. I say worst case because for the LC filter this doesn’t prevent the resonance problem. So to prevent the LC resonance, I added a parallel 1 Ohm resistor R1 with the inductor L1. In simulation L1 and C2 forms a very nice high freq. filter. Then I use this LT1086 as an LDO. Here is its datasheet and in applications it is mentioned that it is also recommended for SMPS switching noise filtering(it says "Post Regulators for Switching Supplies"). R2 and Rp set the output to around 12V for a 15V input. Rp can be a potentiometer to fine-tune the output voltage. According to the datasheet if I’m not mistaken the C1 is needed to be a tantalum capacitor and C3 is a ceramic capacitor both with low ESR.

Now I have made transient analysis in LTspice for this filter where the input is 15VDC with 1V pulse noise (with 10p rising falling edges) superimposed on it. So I repeated the same procedure for different noise pulse frequencies 50Hz, 100Hz, 1kHz, 100kHz, 1MegHz.

Below are the simulation results for input and output for these frequencies:

At 50Hz:

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At 100Hz:

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At 1kHz:

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At 100kHz:

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At 1MegHz:

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The results are peak to peak amplitudes at the output for 1V pulse input noise at different frequencies. And here are the results for each:

50Hz ------> 1.6mV

100Hz -----> 3.8mV

1kHz ------> 173uV

100kHz ----> 41uV

1MegHz -----> 1uV

Here is the power dissipation for the regulator which is around 0.5W:

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And finally here below is the current drawn from the SMPS and flow through input stage:

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My questions are:

How can I reduce this supply current? Apparently it is 6A. Obviously there is something wrong with this even though the filtering looks fine. Never made such filter before for such purpose. I would be glad to hear any other fundamental issues for this circuit. SMSP cannot handle more than 500mA or maybe 1A, so reducing C2 can be an option but that degrades the filtering.

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  • \$\begingroup\$ How can I reduce this supply current? Apparently it is 6A That's because you put Vnoise across 20 mohm + 1 ohm + 4700 uF (basically a short). That will result in a large current. Another point: include the ESR of the capacitors, especially for the 4700 uF cap. parasitics are needed because 4700 uF caps have terrible behavior at high frequencies like the ones coming from an SMPS. Consider adding 100 nF and 1 nF ceramic caps in parallel with the 4700 uF to make it "better", see: youtube.com/watch?v=BcJ6UdDx1vg \$\endgroup\$ – Bimpelrekkie Feb 6 '19 at 12:16
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    \$\begingroup\$ I think you're overestimating the amount of noise from the SMPS. You have to determine how much noise the SMPS actually generates and think how much noise reduction you really need (yes, that's hard!!!). Also it is easier to do an FFT (Fourier transform) on the noise of SMPS and LDO as that would show you a spectral plot of the noise. Uhm yeah, this isn't an easy subject. \$\endgroup\$ – Bimpelrekkie Feb 6 '19 at 12:25
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    \$\begingroup\$ 1V is too much for a real scenario? That depends (again, it is not easy), if you have a very poor SMPS, 1 V might be realistic. Some other SMPS might have only 10 mV of noise. It depends. \$\endgroup\$ – Bimpelrekkie Feb 6 '19 at 12:28
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    \$\begingroup\$ C2 is INSANE, it might be reasonable for a line frequency transformer/rectifier/filter sort of supply, but a halfways decent switcher should have half of nothing down that close to DC, and at 100Hz or so a well thought out LDO will have PSRR for days. My usual switcher cleaning filter for mid band is 1uH || 3R + a couple of 0.047uF on the end of an inch of trace (Stolen from "High speed signal prop."), works well given typical parasitic values and gets you ~20dB from a few Mhz. I would second Bimpelrekkie, figure out what you need, then design it (And model the parasitics). \$\endgroup\$ – Dan Mills Feb 6 '19 at 22:50
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    \$\begingroup\$ Also, 100ps rise and fall times? From 0.02R source? I hope that switcher is Real close to the filter because 100ps edge rates make almost any amount of wire into a transmission line, and I ain't never seen a 0.02R characteristic impedance line yet. Spice is an excellent numerical solver, but it relies upon the operator to put sane number into it. \$\endgroup\$ – Dan Mills Feb 6 '19 at 22:54
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The approach is sound, with a problem: you have created a very "stiff" noise source capable of both driving and sinking whatever current is necessary to sustain its voltage. If you think about how SMPS circuits work, you will probably agree that they themselves are charging internal elements and discharging them into the load rather than presenting a low-output-impedance voltage at two distinct levels. If you don't want to simulate the output stage of your SMPS, I would suggest that you try a triangle wave for your noise source as a better analog for the SMPS output, without R1 in your circuit but with a series resistor for your inductor's resistance.

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