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How can I multiply a signed number to unsigned number in verilog for example:

a = 6'b111111 ; //which is means -1 as it is signed

b = 6'b111111 ; //which is means 63 as it is unsigned

I want the result be -63 which is 1000001 which is signed number

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  • \$\begingroup\$ do you mean adding, or multiplying, there's a big difference? Please alter your title, or your question text. \$\endgroup\$ – Neil_UK Feb 6 at 14:05
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The width of your expression is very important when dealing with signed arithmetic. To multiply two 6-bit numbers and get a result of -63, you need at least 7 bits. You also need a to be sign extended to 7 bits. However, in Verilog, whenever you mix signed and unsigned operands, you get an unsigned result. So you need to convert b to at least a 7-bit signed value. You can do that as shown below:

module top;
   bit signed [5:0] a = -1;
   bit [5:0]        b = 63;
   bit signed [6:0] c;

   initial begin
      c = a*$signed({1'b0,b});
      $display("%b %d",c,c);
   end
endmodule
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