Why is the RESET pin set up like this in this Z80 schematic?

Question

I've found the following schematic:

Which after a lot of datasheet reading I mostly understand.

The main thing I don't understand, however, is what's going on with the RESET pin. First of all, I understand that the RESET pin is active-low. In this case, why is it pulled high to +5V? Surely I wouldn't want the CPU to reset. I assume the answer to this part is something to do with resetting on boot.

My main question is why there's a capacitor from RESET to (what seems to be) ground.

Is that even ground? If so, why is there a capacitor before it? If not, what is it, and what does it do?

Answer 1

The Reset pin is Active low, so has to be pulled low to reset the processor.

The capacitor connected to the reset pin is also connected to Gnd (the schematic uses a wrong symbol), and along with the pullup resistor forms an RC network that holds the processor in reset for a time after VCC first rises.

You will often see Reset circuits such as this:

^{simulate this circuit – Schematic created using CircuitLab}

The RC values are defined to hold the processor in reset long enough to let the supply stabilize. It can also provide a physical reset button to reset/restart the processor.

Answer 2

As you have correctly stated, RESET is active low.

On power up C is discharged, the reset is held low which forces the chip to hold off initialising while the power stabilises.

After a time roughly equal to R x C (s) the capacitor voltage has charged up through R enough to release the RESET and allow the controller to run. By this time the power should be stable.

Answer 3

This reset circuit is perfectly adequate for the Z80. The capacitor is initially discharged, so on power-up the /reset input will initially be pulled low, and then rise to 5v. As long as it is low for 4 clock-cycles or more, the Z80 will be reset properly. If the CPU is running at 4MHz then 4 clock cycles is 1/1000000th of a second, so a very wide range of values for the capacitor and resistor will achieve this. If it is held low for longer than 4 cycles it makes no difference at all. The /reset input is LEVEL triggered, not edge triggered, so the CPU will stay in a "being reset" state until the input rises above a certain level. /nmi is edge-triggered, but /reset is level triggered.

Answer 4

This is the simplest circuit to perform a RESET. Note that for a few years, a specialized circuit was also used to carry out a "clean" RESET.