I am hoping if some expert in timing analysis could answer on this topic.
Here is the question:
I am creating a liberty timing file for an IP block using ETM (Extracted Timing Model) method. Accordingly, I have the min_pulse_width parameter for my clock pin extracted by the tool using this ETM method (I input Verilog netlist and SDC to the tool for this extraction).
Tool documentation says that the parameter "min_pulse_width" is extracted for the clock pin using the following formula -
MAX(Arrival time at launch flop - Arrival time at capture flop + min pulse width of library cell) -- for all the paths in the design.
This means there is a relationship between clock skew at a REG-REG path and the min pulse width of my capture FF cell.
I want to exactly understand how they are related ? Can someone give an intuitive explanation for why the tool would extract min_pulse_width for clk pin this way and also talk about relationship between clock skew and pulse width ?