# What does these Verilog line of code mean?

and I've found two lines of code that I don't fully understand:

          if (| count[13:0]) begin


and

  assign data_addr_out_of_range = | data_addr[26:25];


I know that the symbol |, means Bitwise OR and Reduction OR. But I continue without understanding the meaning in those lines.

• Try to think of |x as x != 0. – Vovanium Feb 8 at 0:23

These are reduction-ORs as you suspect. It is a unary operator, whose result is the result of OR'ing all of the bits in the operand. For example, supposing that x is declared reg[3:0] with value 4'b0011, |x is 1 while |x[3:2] is 0.

The first line indicates, "if any bit in count[0:13] is set, then perform the following block". The second indicates that data_addr_out_of_range is 1 if data_addr[26] is 1 or data_addr[25] is 1.

This is an example of poorly written code. The person who wrote it is thinking too much about the implementation, and not writing it at the RTLevel. Much better would be to write this as

if (count) begin


or

if (count !=0 ) begin


Anther problem is the variable count declared as

 reg [13:0] count;


and then referenced everywhere as count[13:0]. (Other variables are used the same way)

If you meant to use the entire variable, you should not add the extra part select. That way shows the intent better. The way this is originally written, if you ever change the width of count you have to go through the code and make sure you change it everywhere it's used.