# VHDL clock divider

I dont really understand the below code, for rising edge of the clock a divider of 4 bits will be incremented, so: 0000 -> 0001 -> 0010 -> 0011 For each rising edge of the clock?

What is div(2)?

If you run a simple simulation (which you will need to learn how to do if you're going to be working with VHDL) you'll see that div only updates on the rising edge of the clock. This means that div(0) is 1/2 the clock rate, div(1) is 1/4 the clock rate, and div(2) is 1/8 the clock rate.

Normally, I'm not in the habit of posting code, but the testbench for simulating this is so trivial I might as well. Note: I've replaced the std_logic_vector type on cnt and div with an unsigned type since addition of std_logic_vectors uses non-standard libraries (or VHDL2008).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk_div is
end clk_div;

architecture TB of clk_div is
signal clk      :   std_logic; -- 200MHz clk
signal cnt      :   unsigned(2 downto 0) := (others => '0');
signal div      :   unsigned(3 downto 0) := (others => '0');

begin

--create 200MHz clock
process
begin
clk <= '1'; wait for 2.5 ns;
clk <= '0'; wait for 2.5 ns;
end process;

process(clk)
begin
if rising_edge(clk) then
div <= div + 1;
end if;
end process;

process(div(2))
begin
if rising_edge(div(2)) then
cnt <= cnt + 1;
end if;
end process;

end TB;

• Really appreciate you writing the code, thank you so much. Ill take a look through it tomorrow – user212221 Feb 8 '19 at 3:03
• Which development environment did you use to run this code, is it ISE xilinx? – user212221 Feb 8 '19 at 9:23
• Also, i wanted to ask. Would the div signal be exactly the same as the clock but for each rising edge there would be a count increment? – user212221 Feb 8 '19 at 9:43
• I ran the simulation in Aldec Active-HDL. For the purposes of simulation, yes it is exactly the same as the clock only 1/8 the frequency. In actual hardware you would have to write a constraint telling the tools to treat div(2) as a clock and then put it on a clock net. In most cases though in real hardware you'd just use a PLL or similar to generate the clock you need. – ks0ze Feb 8 '19 at 16:01

div(2) is the 3rd bit of the vector div.

Your VHDL has two processes the first increments the vector div (considered as an integer) on every rising edge of clk.

The vector div is 4 bits long (3 downto 0) you can refer to each of the 4 bits of div as div(3) div(2) div(1) and div(0).

when div is 0100 div(3) is 0, div(2) is 1, div(1) is 0 &c.

the second process works exactly the same except the counter it incremements is called cnt and it's incremented on the rising edge of div(2) (which is 1/8 th the frequency of clk).

• Wouldnt it be 1/4 of the frequency of the clock? 1: 0 2: 1 4: 0 8: 0 The rise and fall of the 2nd bit counting from 0 from the LSB of 0100 occurs every 4 rising edges of the clock – user212221 Feb 8 '19 at 2:20
• Isnt the divider 1/4 of the clock frequency? – user212221 Feb 8 '19 at 2:24
• @YaGetMeh, No, 1/8 is correct. div(0) would be 1/2 because it only toggles on rising edges of the clock, div(1) toggles every other rising edge, and div(2) toggles every 4th rising edge – ks0ze Feb 8 '19 at 2:27
• @james, The sensitivity lists are correct as is. Process 1 can only update on the rising edge of clk and process 2 can only update on the rising edge of div(2) – ks0ze Feb 8 '19 at 2:31
• If it toggles on rising edges of the clock, when does it fall/untoggle? – user212221 Feb 8 '19 at 2:34