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I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out what mistake I'm making will be much appreciated!

module test (i_clk, ctr, o_wf);
parameter size = 4;
input wire [(size-1):0]ctr;
input wire i_clk;
output wire o_wf;

reg msb;

initial msb <= 1'b0;
always@(posedge i_clk)
    begin
        msb <= ctr[(size-1)];
    end
assign o_wf = msb;
endmodule

`timescale 1ns/1ps
module test_tesbench;
    parameter size = 4;
    reg i_clk;
    reg [(size-1):0]ctr;
    wire o_wf;

initial 
    begin 
        i_clk <= 1'b0;
    end

test DUT(.i_clk(i_clk), .ctr(ctr), .o_wf(o_wf));

always
    begin
        #(0.1) i_clk <= ~i_clk;
    end

always@(posedge i_clk)
    begin
        ctr <= ctr + 1'b1;
    end
endmodule

All counter bits are shown as X

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  • \$\begingroup\$ You have the simulation...just trace the X back through your logic. At some point you will see something that is obviously incorrect. Learning how to debug with a simulator is much better than debugging source code by inspection. \$\endgroup\$ – Elliot Alderson Feb 9 '19 at 13:29
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You have never initialized the counter.

In contrast to normal programing languages all Verilog variables have an initial value of 'X'.
(In VHDL the value 'U').

You then perform an add but X + 1 still produces X.

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