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we need to enable a register to write into that register, which is done using a decoder.
even if we enable 1 register using decoder, given that RD(bar) is 0, all registers can still produce an output. And if all registers can respond, output would get corrupted.
so would we not need to select the output of that register , maybe by multiplexing?
is multiplexing used between output buffer and memory in this figure ? is it something else? i am not able to find on the net enter image description here

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  • \$\begingroup\$ because only the addressed register will output to the bus. That's the idea of adressing, after all. \$\endgroup\$ – Marcus Müller Feb 9 at 14:31
  • \$\begingroup\$ i understand that only the addressed register is enabled hence , only that register can be written onto. but to read from that register we don't need to enable it, right? since to read from registers we don't need to enable them, all registers can respond to the output buffer. hence the need for a multiplexer? \$\endgroup\$ – abhishek Feb 9 at 14:35
  • \$\begingroup\$ What is most concerning me is the statement " i am not able to find on the net". Just as a warning: You will find that not every answer is available on the internet. However when I tried "multiplex cpu bus" (images) I did find the answer. \$\endgroup\$ – Oldfart Feb 9 at 14:36
  • \$\begingroup\$ @Oldfart i understand how address and data buses are multiplexed.i understand this figure. what i am asking is different.i have included a figure in my question to clarify. \$\endgroup\$ – abhishek Feb 9 at 14:52
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There is implicit multiplexing, created by providing each register with a 3-state output driver, and enabling only one driver at a time onto the bus. That's why you see the \$\overline{\text{RD}}\$ and \$\overline{\text{CS}}\$ lines connected to the Output Buffers in your diagram. The buffers are only enabled when \$\overline{\text{RD}}\$ and \$\overline{\text{CS}}\$ are both low at the same time.

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  • \$\begingroup\$ (refering to the eprom diagram) so if each register has a 3-state output driver, the output driver of that register would need to be selected in addition to selecting that register. so is the output driver selected using the internal decoder or something else.Could you add a diagram? \$\endgroup\$ – abhishek Feb 10 at 5:46

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