# Signed and unsigned numbers in verilog

I understand the concept of fixed point and multiplying signed with unsigned by sign extension the unsigned number with 1 bit of '0' so it will be signed always positive number, But my question

If I want to multiply -186 which is '1101000110' with a fraction 6-bit number of 0.5 which is '100000'

So I want to sign extend the fraction number to be '0100000' so this fraction number will it seen as 0.25 not 0.5 !

In other words how can I write 0.5 in signed always positive number

• uh, what? If you sign-extend 0.5 it stays 0.5, it doesn't become 0.25. – Marcus Müller Feb 10 at 8:48

You are making the mistake of "shifting" the number right when adding zeros to the front.

Let me give you the equivalent in decimal.

If we take the number 5 we can add as many zero to the front as we like. Thus 5, 05, 005 etc. are all the same number. If I write that up 'aligned' we would see:

    5
05
005


Most people are more familiar with this notation in fractional format:

    5.0
05.0
005.0


Thus the position of the decimal point stays the same. When you are multiplying you also have to 'align'** the numbers:

1101000110.000000
.100000 x
-----------------


Now you can add zeros to the front and end up with:

1101000110.000000
0000000000.100000 x
-----------------


**This way of alignment for multiplication is the way I have been taught in my country. I don't know how universal that is.