According to this datasheet of a SDRAM module it has 2 banks of 524,288 memory locations, but only a 11 bit (\$2^{11}=2,048\$) address bus.

  • How can an address bus with only 11 bits access all those memory locations?
  • Does it access rows and columns of the memory separately?
  • \$\begingroup\$ There is an ACCESS command which specifies the 11-bit row and a READ or WRITE command which specified the remaining 8 column bits. Also, there is a separate bank select, only two of them, which chooses the bank. So this totals to 19 bits plus 1 bit for the bank and therefore about total of 20 address bits. That is all that is needed. \$\endgroup\$
    – jonk
    Feb 11 '19 at 8:05
  • \$\begingroup\$ @jonk very straight forward explanation. Thank you. \$\endgroup\$
    – nilleeee
    Feb 11 '19 at 8:32

Does access rows and columns of the memory seperately?


This is more obvious in the older DRAM of which SDRAM is an evolution. It has separate Row and Column strobe, multiplexing the same address pins for two ranges. You first set the row you want, assert the Row Address Strobe (RAS). Then you change the address pins to the column you want and assert the Column Address Strobe (CAS).

This method is still used with SDRAM and DDR, and the pins are there, but they are now called "commands" because there are more combinations.

  • \$\begingroup\$ Thank you very much for your answer. Is there a rule of thumb what types of memory utilize multiplexing? Most other websites I googled just state that the width of the address bus determines the accessible memory locations without mentioning the possibility of multiplexing. \$\endgroup\$
    – nilleeee
    Feb 11 '19 at 8:18
  • 1
    \$\begingroup\$ @nilleeee Essentially everything called DRAM (SDRAM,DDR) will have Row/Column multiplexing, simply based on the details on how they are constructed. I have never seen SRAM with a multiplexed address bus, although serial SRAM could be interpreted as an extremely multiplexed bus that sets one bit at a time! \$\endgroup\$
    – pipe
    Feb 11 '19 at 8:25
  • \$\begingroup\$ Thanks again for your response. That clears things up! \$\endgroup\$
    – nilleeee
    Feb 11 '19 at 8:27

The datasheet describes how to select bank, row, and column:

The Bank Active command is used to activate a row in a specified bank of the device. […] The value on the BA selects the bank, and the value on the A0-A10 selects the row.
The READ command is used to initiate the burst read of data. […] BA input select the bank, A0-A7 address inputs select the starting column location.

So there are 21+11+8 = 220 possible addresses.

  • \$\begingroup\$ Thank you very much. That was very helpful. I shouldn't just skip the fine print. \$\endgroup\$
    – nilleeee
    Feb 11 '19 at 8:26

On page 8 it states:

Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns
by 32-bits

And 11-bit = 2048 so the 11-bit Address bus is sufficient to select any of the rows (I'm not saying it actually works like that).

But how do we select the columns?

We use the same 11-bit Address bus again. The rows and columns are not selected at once but separately and the separation is done in time. Note how there is a certain sequence to be observed when addressing the data!

Theoretically even a 1-bit (instead of 11-bit) address bus could be used to address any of the bits on a memory chip with the same capacity by sending the address information in a serial way, so one after the other. Yes, that would not be fast (it would be slow) but it can work.


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