Design the VHDL components (Register, Decoder, and two Multiplexer 16 bit) and interconnect them to build a register file. The schematic shows only four registers. Your solution should implement eight registers.

enter image description here

The diagram provided as a example uses a 2:1 and 4:2 multiplexer, this dealt with 4 bits. Now that I've to create a circuit with 16 bits, what are my inputs into the multiplexer, in relation to vhdl code?

I've completed a sketch of the circuit, am I correct? enter image description here

I did the VHDL code for the first multiplexer

library IEEE;

entity mux8_16 is   

    Port(in0,in1,in2,in3,in4,in5,in6,in7: in std_logic_vector (15 downto 0);  
         s0, s1, s2: in std_logic (1 downto 0);   
         z: out std_logic_vector (15 downto 0));  

end mux8_16;  

architecture behavioural of mux8_16 is  

z <= in0 after 5ns when s0 = '0' and s1 ='0'  and s2 ='0'else  
     in1 after 5ns when s0 = '0' and s1 ='0'  and s2 ='1'else   
     in2 after 5ns when s0 = '0' and s1 ='1'  and s2 ='0'else   
     in3 after 5ns when s0 = '1' and s1 ='0'  and s2 ='0'else   
     in4 after 5ns when s0 = '0' and s1 ='1'  and s2 ='1'else  
     in5 after 5ns when s0 = '1' and s1 ='0'  and s2 ='1'else   
     in6 after 5ns when s0 = '1' and s1 ='1'  and s2 ='0'else  
     in7 after 5ns when s0 = '1' and s1 ='1'  and s2 ='1'else   
     '0000000000000000' after 5ns  

end behavioural;  

Is the code the right format? For the decoder is this correct?

entity decoder_3to8 is  
        Port(din:in std_logic_vector(2 downto 0);  
        dout: out std_logic_vector (7 downto 0));  
end decoder_3to8;  
architecture behavioural of decoder_3to8 is  
     dout <=    ("10000000") when (din="000") else   
                ("01000000") when (din="001") else   
                ("00100000") when (din="010") else   
                ("00010000") when (din="011") else   
                ("00001000") when (din="100") else  
                ("00000100") when (din="101") else   
                ("00000010") when (din="110") else  
                ("00000001") ;   
end behavioural;    

Is this code correct for the instance of a regsiter?

   architecture GEN of REG_BANK is     
   component REG     
    Port(Load,Clk,D :in std_ulogic;    
        Q : out std_ulogic);    
end component;    
    for I in 0 to 7 generate     
        REGX : REG port map    
           (LOAD,CLK,DIN(I), DOUT(I));       
        end generate GEN_REG;     
end GEN;     
  • \$\begingroup\$ Why not start by putting 8 registers instead of 4, and expanding the input decoder and output mux to make them handle 8 ways? Also expand the width of all data busses to 16. Done. \$\endgroup\$ – dim Feb 11 at 14:31
  • \$\begingroup\$ Okay I''ll do that now, however do you mean change 4 registers to 8 registers? does that mean I'll have one 8:1 multiplexer and then a 2:1 \$\endgroup\$ – Sue Feb 11 at 14:34
  • \$\begingroup\$ @dim also is (3:0) for all eight registers and multiplexers? \$\endgroup\$ – Sue Feb 11 at 14:37
  • \$\begingroup\$ Yes, I didn't read the text very carefully. I mixed the bit width and the number of registers (I updated my comment). As I understand, you need both to increase the number of register to 8 and the bit width to 16, right? (it's not quite clear) So you need a decoder_3to8 instead of the 2to4 and probably a mux8_16bit instead of the mux4_4bit and a mux2_16bit instead of the mux2_4bit. If these basic blocks aren't there, you need to make them out of smaller ones, but you know how to do that, right? \$\endgroup\$ – dim Feb 11 at 14:40
  • \$\begingroup\$ Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. \$\endgroup\$ – Dave Tweed Feb 11 at 14:41

Since this is clearly homework, I'm just going to provide hints that guide you toward a solution:

Perhaps you should start by writing the VHDL for the circuit as shown. Then, try to understand which parts of the code pertain to the width of the data buses, and which parts pertain to the number of registers.

  • \$\begingroup\$ I provided my solution, on which I think the circuit should look like, do I have the right idea? \$\endgroup\$ – Sue Feb 11 at 15:07
  • \$\begingroup\$ Yes, that's the general idea. Now turn it into VHDL. \$\endgroup\$ – Dave Tweed Feb 11 at 15:25
  • \$\begingroup\$ I edited the question above with the VHDL, is it correct? \$\endgroup\$ – Sue Feb 11 at 15:29
  • \$\begingroup\$ Almost. The s0, s1 and s2 input ports are single wires -- get rid of the (1 downto 0) in that line. Although it would be more idiomatic to make it a single 3-bit port: s: in std_logic_vector (2 downto 0) \$\endgroup\$ – Dave Tweed Feb 11 at 15:43
  • \$\begingroup\$ I added the code for the decoder, is it correct? \$\endgroup\$ – Sue Feb 11 at 16:20

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