TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi

I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is synthesized with Clk_Period = 2 ns and the timing report of the design shows it could meet the timing completely (slack (MET) = +1.75). To me it means that 2 ns is more than enough to meet the required setup and hold time of each flip-flop from the technology standard libraries. However, after simulating the netlists, it seems it has problem with delivering data from registers in 2 ns and it need the data to be stable for more than that (having 4 ns between two consecutive changes seems to be enough to get data out from the output of register) the following attachment shows this issue:

2- Simulating the netlists versus the SDF back annotated file gives me errors regarding the hold time:

# ** Error: PATH_TO_STANDARD_CELL_LIBRARY_BEHAVIORAL_FILE(25913): $hold( posedge CP:6 ns, negedge D &&& dE:6 ns, 14 ps );
#    Time: 6 ns  Iteration: 1  Instance: :Test_Design_tb:DUT: Register1_reg_2_

All above problems happen while report_constraint -all_violators gives: "This design has no violated constraints." and report_timing shows positive slack for the paths

3- In another design of mine I have a memory IP block. when doing SDF simulation I am getting several issues:

sdf simulation stops with FATAL error (several errors of two different types:

# ** Error (suppressible): (vsim-SDF-3261) PATH_TO_SDF_FILE.sdf(107919): Failed to find matching specify module
# ** Error (suppressible): (vsim-SDF-3262) PATH_TO_SDF_FILE.sdf(107923): Failed to find matching specify timing
** Fatal: (vsim-SDF-3444) Failed to annotate from SDF file PATH_TO_SDF_FILE.sdf
# Time: 0 ps Iteration: 0 Instance: :sram_mult_top_tb File: PATH_TO_TESTBENCH_FILE.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design

using vsim -sdfnoerror to reduce errors to warnings helps running the simulation, however still with following two type warnings (errors reduced to warnings)

# ** Error (suppressible): (vsim-SDF-3261) PATH_TO_SDF_FILE.sdf(107919): Failed to find matching specify module
# ** Error (suppressible): (vsim-SDF-3262) PATH_TO_SDF_FILE.sdf(107923): Failed to find matching specify timing

and running the simulation it has several timing issues for resolving the out values. I am wondering if I really need to modify the sdf content with respect to IP and if so, how?

I appreciate any hint or help about above issues.


I found a *.verilog.map file of the memory IP block which contains a couple of lines of info on TIMINGCHECK struct of SDF file. any comment or hint on how to use it?

Also, I checked the report_timing report of the the design with IP memory. all paths coming into or out of memory block are unconstrained. so, I think somehow the generated sdf file by synthesis tool should be modified. we had a collegue before who had written a perl script to fix some issues with sdf files. unfortunately I do not have any more access to him to ask how and why!


Synthesizing the design with IP memory *.db file using design_vision Synopsys, and then read the generated SDF file by read_sdf FILE.sdf the following warning comes out as the result:

# Warning: Cell delay could not be annotated between pin 'SRAM_WRAPPER/DUT/D2[0]',
# and pin 'SRAM_WRAPPER/DUT/Q2[0]' for the design 'DESIGN_WITH_SRAM_TOP'. (SDFN-6)

# SDF file PATH_TO_SDF_FILE.sdf, line 107904.

# Warning: no lib arc with matching sdf_cond "TBYPASS2" between

NOTE: D2[*] are the input pins to SRAM and Q2[*] are output pins from memory

  • \$\begingroup\$ When you synthesized your design, were you also synthesizing the IP? Or are you using a pre-synthesized IP block? You may not have had the correct timing constraints on the I/Os between the block when you ran synthesis. Your #3 looks like a separate issue. \$\endgroup\$ – Justin Feb 11 '19 at 15:38
  • \$\begingroup\$ #3 is "simply" a file reference issue... I've had issues in the past trying to point to a .sdf file not in the same directory as the simulation (Been a while since I did back-annotation). For the "timing error": Do you have just one clock domain (and this error is not at a crossing), and is your design sequential (i.e. no transparent latches)? Maybe try using -sdfreport=<filename> and see if you gain any further insight. And, if you haven't yet, look at the command line reference for vsim in the "sdf section" for some other possibly useful switches. \$\endgroup\$ – CapnJJ Feb 11 '19 at 16:47
  • \$\begingroup\$ @Justin I used the .db library file of memory in the synthesis flow. otherwise the IP block comes as an unresolved resource to the end. However, I am not sure I got you right about "synthesizing the IP or using a pre-synthesized IP block". Checking the timing report it shows all "(Path is unconstrained)" \$\endgroup\$ – manpmanp Feb 13 '19 at 9:19
  • \$\begingroup\$ @CapnJJ I used -sdfreport switch with vsim command and it shows all pins related to the IP memory are either of the following two types: (UASP) = Unannotated specify path. (UATC) = Unannotated timing check. \$\endgroup\$ – manpmanp Feb 13 '19 at 16:23
  • \$\begingroup\$ @manpmanp Not familiar with those labels, but it sounds like you don't have an .sdf for the IP(?). That would be consistent with the latter issues you reported above in terms of "file path error". I would consider opening a ticket with support.mentor.com/en with the appropriate information from this question and the results you stated in the comments. You can always close it if you solve it on your own, but they are usually good about responding in a timely manner, and you can talk in real-time. \$\endgroup\$ – CapnJJ Feb 13 '19 at 17:54

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