TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi
I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is synthesized with Clk_Period = 2 ns and the timing report of the design shows it could meet the timing completely (slack (MET) = +1.75). To me it means that 2 ns is more than enough to meet the required setup and hold time of each flip-flop from the technology standard libraries. However, after simulating the netlists, it seems it has problem with delivering data from registers in 2 ns and it need the data to be stable for more than that (having 4 ns between two consecutive changes seems to be enough to get data out from the output of register) the following attachment shows this issue:
2- Simulating the netlists versus the SDF back annotated file gives me errors regarding the hold time:
# ** Error: PATH_TO_STANDARD_CELL_LIBRARY_BEHAVIORAL_FILE(25913): $hold( posedge CP:6 ns, negedge D &&& dE:6 ns, 14 ps ); # Time: 6 ns Iteration: 1 Instance: :Test_Design_tb:DUT: Register1_reg_2_
All above problems happen while
report_constraint -all_violators gives: "This design has no violated constraints."
and report_timing shows positive slack for the paths
3- In another design of mine I have a memory IP block. when doing SDF simulation I am getting several issues:
sdf simulation stops with FATAL error (several errors of two different types:
# ** Error (suppressible): (vsim-SDF-3261) PATH_TO_SDF_FILE.sdf(107919): Failed to find matching specify module path. # ** Error (suppressible): (vsim-SDF-3262) PATH_TO_SDF_FILE.sdf(107923): Failed to find matching specify timing constraint. ** Fatal: (vsim-SDF-3444) Failed to annotate from SDF file PATH_TO_SDF_FILE.sdf # Time: 0 ps Iteration: 0 Instance: :sram_mult_top_tb File: PATH_TO_TESTBENCH_FILE.vhd Line: UNKNOWN # FATAL ERROR while loading design # Error loading design
vsim -sdfnoerror to reduce errors to warnings helps running the simulation, however still with following two type warnings (errors reduced to warnings)
# ** Error (suppressible): (vsim-SDF-3261) PATH_TO_SDF_FILE.sdf(107919): Failed to find matching specify module path. # ** Error (suppressible): (vsim-SDF-3262) PATH_TO_SDF_FILE.sdf(107923): Failed to find matching specify timing constraint.
and running the simulation it has several timing issues for resolving the out values. I am wondering if I really need to modify the sdf content with respect to IP and if so, how?
I appreciate any hint or help about above issues.
I found a *.verilog.map file of the memory IP block which contains a couple of lines of info on TIMINGCHECK struct of SDF file. any comment or hint on how to use it?
Also, I checked the report_timing report of the the design with IP memory. all paths coming into or out of memory block are unconstrained. so, I think somehow the generated sdf file by synthesis tool should be modified. we had a collegue before who had written a perl script to fix some issues with sdf files. unfortunately I do not have any more access to him to ask how and why!
Synthesizing the design with IP memory *.db file using design_vision Synopsys, and then read the generated SDF file by read_sdf FILE.sdf the following warning comes out as the result:
# Warning: Cell delay could not be annotated between pin 'SRAM_WRAPPER/DUT/D2', # and pin 'SRAM_WRAPPER/DUT/Q2' for the design 'DESIGN_WITH_SRAM_TOP'. (SDFN-6) # SDF file PATH_TO_SDF_FILE.sdf, line 107904. # Warning: no lib arc with matching sdf_cond "TBYPASS2" between # SRAM_WRAPPER/DUT/TBYPASS2 to SRAM_WRAPPER/DUT/Q2
NOTE: D2[*] are the input pins to SRAM and Q2[*] are output pins from memory