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I am trying to characterize this nmos on Xyce simulator (and trying to change its present Vthreshold) and am first DC sweeping the gate and measuring the current through the nmos.

I run into this strange issue where even if I sweep Vg from 0-1.8V and wire drain/source interchangeably, I find the same current going through the nmos. And it has an unusually high resistance.

Two questions, am I doing wrong with this NMOS? AND, I am using this SPICE 180nm BSIM3 model and cannot find how to change Vthreshold on it. With these models is that generally something one can do?

* NMOS Model 180nm


*********Analysis Commands**************

.DC Vg 0 1.8 0.1

.print DC V(3) I(Vd)


****************************************


*Power Source


Vd 1 0 1.8V

*NMOS device    M<name> <drain node> <gate node> <source node> + <bulk/substrate node> <model name>

M1 0 3 1 0 NMOS180


* sense resistors

;R1 2 0 1k


*Gate voltage

Vg 3 0 0V


*NMOS online model card
.model NMOS180 NMOS(
+Level = 49

+Lint = 4.e-08 Tox = 4.e-09
+Vth0 = 0.3999 Rdsw = 250

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 TNOM=27.0 version =3.1
+Xj= 6.0000000E-08         Nch= 5.9500000E+17
+lln= 1.0000000            lwn= 1.0000000              wln= 0.00
+wwn= 0.00                 ll= 0.00
+lw= 0.00                  lwl= 0.00                   wint= 0.00
+wl= 0.00                  ww= 0.00                    wwl= 0.00
+Mobmod=  1                binunit= 2                  xl=  0
+xw=  0                    binflag=  0
+Dwg= 0.00                 Dwb= 0.00

+K1= 0.5613000               K2= 1.0000000E-02
+K3= 0.00                  Dvt0= 8.0000000             Dvt1= 0.7500000
+Dvt2= 8.0000000E-03       Dvt0w= 0.00                 Dvt1w= 0.00
+Dvt2w= 0.00               Nlx= 1.6500000E-07          W0= 0.00
+K3b= 0.00                 Ngate= 5.0000000E+20

+Vsat= 1.3800000E+05       Ua= -7.0000000E-10          Ub= 3.5000000E-18
+Uc= -5.2500000E-11        Prwb= 0.00
+Prwg= 0.00                Wr= 1.0000000               U0= 3.5000000E-02
+A0= 1.1000000             Keta= 4.0000000E-02         A1= 0.00
+A2= 1.0000000             Ags= -1.0000000E-02         B0= 0.00
+B1= 0.00

+Voff= -0.12350000          NFactor= 0.9000000          Cit= 0.00
+Cdsc= 0.00                Cdscb= 0.00                 Cdscd= 0.00
+Eta0= 0.2200000           Etab= 0.00                  Dsub= 0.8000000

+Pclm= 5.0000000E-02       Pdiblc1= 1.2000000E-02      Pdiblc2= 7.5000000E-03
+Pdiblcb= -1.3500000E-02   Drout= 1.7999999E-02        Pscbe1= 8.6600000E+08
+Pscbe2= 1.0000000E-20     Pvag= -0.2800000            Delta= 1.0000000E-02
+Alpha0= 0.00              Beta0= 30.0000000

+kt1= -0.3700000           kt2= -4.0000000E-02         At= 5.5000000E+04
+Ute= -1.4800000           Ua1= 9.5829000E-10          Ub1= -3.3473000E-19
+Uc1= 0.00                 Kt1l= 4.0000000E-09         Prt= 0.00

+Cj= 0.00365               Mj= 0.54                    Pb= 0.982
+Cjsw= 7.9E-10             Mjsw= 0.31                  Php= 0.841
+Cta= 0                    Ctp= 0                      Pta= 0
+Ptp= 0                    JS=1.50E-08                 JSW=2.50E-13
+N=1.0                     Xti=3.0                     Cgdo=2.786E-10
+Cgso=2.786E-10            Cgbo=0.0E+00                Capmod= 2
+NQSMOD= 0                 Elm= 5                      Xpart= 1
+Cgsl= 1.6E-10             Cgdl= 1.6E-10               Ckappa= 2.886
+Cf= 1.069e-10             Clc= 0.0000001              Cle= 0.6
+Dlc= 4E-08                Dwc= 0                      Vfbcv= -1 )





*****unrecognized parameters ******

;tref -> tnom
;xl   ->  xl  (xyce has but default is zero
;xw   ->  xw  (xyce has but default is zero
;PHP,binflag,N -> hspice specific
;CTA,CTP,PTA,PTP -> not found
;NQSMOD (noin quasi specific model) -> NQSMOD (recommended zero)

And here is the output file that shows current flowing equally in both directions. Both output files show the same current at the same timestep xyce output

UPDATE:

I have tried setting the substrate node to ground in this circuit but still get symmetrical source-drain current behavior.

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  • \$\begingroup\$ On the one hand, I don't see how your output data shows current flowing in two directions --- the sign of the current is always negative. On the other hand, if you keep the body terminal tied to the lowest potential node in the circuit, rather than to the source terminal, then symmetric behavior is exactly what you should expect. \$\endgroup\$ – The Photon Feb 11 at 16:48
  • \$\begingroup\$ That specific figure doesnt show that, youre right. I was just saying that when I run the simulation I get this behavior for both source/drain node configurations. \$\endgroup\$ – user P520 Feb 11 at 17:00
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In a real, physical NMOS transistor fabricated using a planar technology the source and drain terminals are in fact interchangeable. The "source" is therefore the terminal at the lower voltage and the "drain" is at the higher voltage. However, you do want to connect the body to the lowest voltage in the circuit to prevent forward biasing the body/source junction.

You generally cannot change the threshold voltage directly in a BSIM3 model. These models are very complex and with a great deal of interaction between the model parameters.

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  • \$\begingroup\$ If I want it to behave like a "voltage controlled switch with no reverse biasing" eg current flowing from drain to source, do I just need to change the bulk voltage and/or the subtrate node? \$\endgroup\$ – user P520 Feb 11 at 20:09
  • \$\begingroup\$ It sounds like you want to connect both the source and the substrate to the lowest voltage in your circuit. The drain-to-source current will then be controlled by the gate voltage. \$\endgroup\$ – Elliot Alderson Feb 11 at 20:19
  • \$\begingroup\$ Now even after doing connecting source and substrate nodes to ground, I get symmetrical behavior. Is there any explanation of why that would be? \$\endgroup\$ – user P520 Feb 11 at 21:46
  • \$\begingroup\$ What do you mean by "symmetrical behavior"? If ground is the lowest voltage in your circuit then current can only flow from drain to source. \$\endgroup\$ – Elliot Alderson Feb 12 at 12:55
  • \$\begingroup\$ I mean that even if I have source node at VDD and drain node at GND and DC sweep the gate, I am getting the same magnitude of current as if source and drain nodes were swapped. \$\endgroup\$ – user P520 Feb 12 at 18:34
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As @Elliot said, the transistor (because it is symmetrical) does not know which terminal is the drain and which is the source, it is only a matter of potentials.

To reply to your questions:

am I doing wrong with this NMOS?

Not really, results show as expected.

how to change Vthreshold on it

Threshold voltage can only be changed by changing its bulk voltage (see body effect).

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  • \$\begingroup\$ I was expecting to get asymmetrical behavior on the NMOS. Is that then just based on where I place the substrate node? \$\endgroup\$ – user P520 Feb 11 at 20:00
  • \$\begingroup\$ No, if you do not change anything else than the source and drain nodes, you will still get the same symmetrical behaviour, independent on the bulk voltage. The bulk voltage will change the threshold as shown in the reference, it does not interfere with the symmetry of the transistor. You can also read further into some validation here \$\endgroup\$ – Alberto Feb 12 at 0:54

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