I would like to interface a FPGA with a fairly fast IC. My FPGA is MachXO2-7000HC while the IC in question is FTDI's FT601, which is a USB 3.0 to FIFO bridge.
The FT601 has quite a few control/data signals, totaling 42 signals (32 data lines plus 10 control signals used for controlling the actual transactions). The data lines are bidirectional and the incoming clock from the FT601 is 100 MHz, which is quite fast.
I am using the MachXO2 TQFP-144 version, which consists of 6 banks, 1 at the top, right and bottom and 3 at the Left side. My original plan was to interface with this IC using Bank 1, which resides at the right of the MachXO2 FPGA chip.
Then, I realized that each bank at Top, Left and Bottom consists of 27-29 I/Os which are less than those required by the FT601, so I will have to "borrow" some I/Os from a neighbor bank.
So my questions are:
- Is it legitimate to use two different banks to interface with an IC?
- Is it considered a generally safe practice or should be avoided?
- Is it going to affect the IO speed somehow since those are different banks?
I am worried since the IC has high speed requirements plus a large number of data and control lines.
Of course both banks will be configured with the same power source as well as the same I/O Type. (FT601 uses 3.3V bidirectional I/Os, outputs 100 MHz for the controller [FPGA], Single Data Rate)
Lastly, I carefully studied both the MachXO2 Family Datasheet as well as the MachXO2 sysIO Usage Guide and did not read anything that explicitly discourage it or a section that implies that it will cause any issues.
Thanks in advance.