I would like to interface a FPGA with a fairly fast IC. My FPGA is MachXO2-7000HC while the IC in question is FTDI's FT601, which is a USB 3.0 to FIFO bridge.

The FT601 has quite a few control/data signals, totaling 42 signals (32 data lines plus 10 control signals used for controlling the actual transactions). The data lines are bidirectional and the incoming clock from the FT601 is 100 MHz, which is quite fast.

I am using the MachXO2 TQFP-144 version, which consists of 6 banks, 1 at the top, right and bottom and 3 at the Left side. My original plan was to interface with this IC using Bank 1, which resides at the right of the MachXO2 FPGA chip.

Then, I realized that each bank at Top, Left and Bottom consists of 27-29 I/Os which are less than those required by the FT601, so I will have to "borrow" some I/Os from a neighbor bank.

So my questions are:

  • Is it legitimate to use two different banks to interface with an IC?
  • Is it considered a generally safe practice or should be avoided?
  • Is it going to affect the IO speed somehow since those are different banks?

I am worried since the IC has high speed requirements plus a large number of data and control lines.

Of course both banks will be configured with the same power source as well as the same I/O Type. (FT601 uses 3.3V bidirectional I/Os, outputs 100 MHz for the controller [FPGA], Single Data Rate)

Lastly, I carefully studied both the MachXO2 Family Datasheet as well as the MachXO2 sysIO Usage Guide and did not read anything that explicitly discourage it or a section that implies that it will cause any issues.

Thanks in advance.

  • \$\begingroup\$ You can safely use different banks without any impact unless you want to control each bank separately in terms of power management or similar. \$\endgroup\$ – Eugene Sh. Feb 12 at 14:52
  • 3
    \$\begingroup\$ It is not unusual to use multiple banks for a single interface; you do need to consider simultaneous switching output power, though. Each bank has it's own supply rail and will have a maximum current it can withstand and you need to make sure you will not exceed that current. \$\endgroup\$ – Peter Smith Feb 12 at 15:01
  • \$\begingroup\$ @PeterSmith Thanks for answering and many thanks for pointing out that I must consider about the power! It's something I hadn't think of, and I am really grateful when more experienced engineers help me develop my skills like that, since I am relatively young in the field. I checked both datasheets, the chips seem compatible regarding the power while switching. \$\endgroup\$ – Manos Feb 12 at 18:42

It depends. If you aren't using any specialized hardware features and the bank power supplies are the same IO voltage, then there are usually no issues.

Things you might have to watch out for if you want to split an interface across banks:

  • Bank IO voltages and IO standards. If you need the same IO standard across the interface, then you'll probably need to have to connect the same supply voltage to both banks. There are some exceptions to this, check the device datasheet to see what IO standards are supported at what IO supply voltages. Devices may have a wider selection of input IO standards and things like LVDS may be supported at multiple bank voltages.

  • Dedicated IO clocking resources. Things like DDR flip flops and IO serdes blocks can require specialized clock routing resources to bring in high speed and/or low skew clocks. These clocks can usually only be routed within a bank or to an immediately adjacent bank. Usually something to watch out for with source synchronous IO, almost certainly on the receive side, but also possibly the transmit side, depending on bit rate and device primitives.

  • Regional clocks. Similar to dedicated IO clocks, but can also clock logic. If you need a regional clock for whatever reason, you may be limited in terms of what IO banks you can use based on where the regional clock is driven from and what it is connected to. Usually something to watch out for with source synchronous IO, almost certainly on the receive side, but also possibly the transmit side.

  • Specialized IO primitives. Similar to dedicated IO clocking, but more device specific. See things like Xilinx "native mode" bit slice primitives. Clocks and signals may have to be connected to specific pins in specific ways within a bank.


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