I'm designing a computer using a Z80 CPU. I have one EEPROM chip and two RAM chips, so far. I have to do things like this:


To ensure that this specific RAM chip is only enabled when the 13th and 15th bits of the address are high, and the 14th is off.

This, however, seems very messy. Is there a standard way of doing this, which involves minimal (or no) logic gates?

EDIT: Here's the schematic I came up with, if anyone's trying to work this out in the future:



2 Answers 2


The standard way is to use at least one demultiplexer, such as a a 74LS238.

It basically implements the same logic you have put together but for multiple different outputs at a time.

Some designers choose to not fully decode the address space, leaving “images” of the same locations across memory. In some cases this can be useful, but it can lead to hard to diagnose bugs and bus contention if you are not careful.

In some microprocessors careless decoding can lead to some instruction sequences completely locking the bus.

  • \$\begingroup\$ The 74LS238 look very useful. Could you provide a simple schematic showing how it's used? \$\endgroup\$ Commented Feb 14, 2019 at 8:39
  • 1
    \$\begingroup\$ It is probably the '138 that you actually want, CS pins generally being active low and all. You tie A13,14,15 to the A inputs on the '138, connect MREQ* to one of the appropriate enable inputs and get 8 active low memory chip selects out the other side, simples. \$\endgroup\$
    – Dan Mills
    Commented Feb 14, 2019 at 22:19

You don't have to fully decode the address, as long as you are very careful when you write your code.

For example, just use A15 for the CE2 of the EEPROM. The address space for the EEPROM will then be from 0x8000 to 0xFFFF (whether you need that much space or not). Then make damn sure that whenever you address the RAMs you have A15 set to zero. For the RAMs you can then use A14 and/or A13 as chip select lines...I can't be more specific without seeing the data sheet.


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