I am trying to implement AES in verilog using 32-bit data path, but I am not able to subsitute the 128-bit in just four clock cycles, my code requires five clock cylces, Here is the small portion of code;
assign initialXorKey = addroundkey(plain_text,cipher_key); assign mixOut = mixw(r0_new,r1_new,r2_new,r3_new); assign shiftRow= shiftrows(mixOut); always @(posedge clk or negedge reset_n) begin if(!reset_n) begin count<=0; subCount<=0; end else begin sboxIn<=sboxNext; subCount<=subCount+1; if(subCount==2'h3) count<=count+1; end end always@ (*) begin case(subCount) 2'h0: begin if(count==0) sboxNext=initialXorKey[31:0]; else sboxNext=shiftRow[31:0]; r3=sboxOut; r0_new=r0; r1_new=r1; r2_new=r2; r3_new=r3; end 2'h1: begin if(count==0) sboxNext=initialXorKey[63:32]; else sboxNext=shiftRow[63:32]; r0=sboxOut; end 2'h2: begin if(count==0) sboxNext=initialXorKey[95:64]; else sboxNext=shiftRow[95:64]; r1=sboxOut; end 2'h3: begin if(count==0) sboxNext=initialXorKey[127:96]; else sboxNext=shiftRow[127:96]; r2=sboxOut; end endcase end
since the new value on right hand side register in is reflected on the next clock cycles, the output of S-Box comes on next clock cycle, since it a recursive process (i.e after fourth clock cycles I have to run the Subsition for the next 128-bit which depends also depends on the current subsituted 128-bit). I am bounded to do it in only four clock cycles and people did it. I am not sure how to fix this, but help is greatly appreciated.