We are considering to have the following stackup for an 8-layer PCB we are designing.
What we want with this stackup is to route the signals with approx. rise time of 3ns on layer 6 using a separation between traces of 8mils between them to get a crosstalk coefficient around -26dB.
- Is the 3mil spacing between Lyr5&Lyr6 and between Lyr6&Lyr7 common?
- Do you guys see any possible electrical or manufacturing problem with this stackup?