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We are considering to have the following stackup for an 8-layer PCB we are designing.

enter image description here

enter image description here

What we want with this stackup is to route the signals with approx. rise time of 3ns on layer 6 using a separation between traces of 8mils between them to get a crosstalk coefficient around -26dB.

Questions:

  1. Is the 3mil spacing between Lyr5&Lyr6 and between Lyr6&Lyr7 common?
  2. Do you guys see any possible electrical or manufacturing problem with this stackup?
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    \$\begingroup\$ Following @Elmesito good answer, you need to work with your chosen PCB fabricator. This isn't a simple 2 or 4 layer job that can be thrown at any PCB fab; the materials & foils available vary from fab to fab, but you have very specific parameters - so you need to choose your fab first, then get their specific stackup advice for their fab service, then proceed with your design. \$\endgroup\$
    – Techydude
    Feb 15, 2019 at 17:12
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    \$\begingroup\$ -26dB is poor for crosstalk, how about -60dB? what is your ripple spec? Do you care about cumulative crosstalk and glitches? Are you going with 5/5 or 3/3 mil track/gap? This layout is far from ideal for size and cost for this performance \$\endgroup\$
    – Tony Stewart EE75
    Feb 15, 2019 at 17:19

3 Answers 3

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To answer your questions:

  1. Using thin prepregs is not uncommon, and in your case for example the standard 1080 prepreg is close to your 3mils thickness. ( a list of the most common thicknesses can be found here)

  2. The issue I see is that you are using a buildup construction, which non all manufacturers are comfortable with using. Another thing that is worth pointing out is that you have an asymmetric layer distribution, which means that you have the risk of having issues with the board flatness, after the assembly process. You might end up with a board that is shaped like a banana.

What I suggest is that you contact your manufacturer of choice, and get them to approve your stacking, making sure you specify what are the limitations that you require. That is the only way you will get the answer you need.

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AFAIK the "stackup" will be called a "layup" at the PWB shop.

your problem for the calculation you're making is it doesn't have tolerances. you need to find the worst case because it will be the first production lot. everything is variable including Er as the glass/epoxy ratio varies. You need to nail down the corner cases. You also have a lot of unexplored questions because you don't really need a coefficient, you need a noise margin and the devil is in the details of the split plane and any issues with ground plane inductance running through zones with too many PTHs and how much if any copper remains on the planes at min hole spacing.

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In the end, we decided to continue with only six layers. We quoted with the PCB manufacturer and they told us that going from 6 to 8 layers would increase the cost of the PCB by almost 200%. We were able to continue with 6 layers and the stack-up that we decided to use is the following:

Final PCB stack-up

enter image description here

This project uses a metallic grounded enclosure. We were able to route "high-frequency signals" mostly on layer 3 and some of them on layer 1 and 4.

Thanks,

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