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schematic

simulate this circuit – Schematic created using CircuitLab

P-Mosfet Datasheet

The goal is that 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2. That 0V (or logic low) appears on U3 when there is logic high on U4 and logic high on U2 or logic low on U2 independantly of U4

I'm using the P-MOSFET (BSS84P), SOT32-2, on hand soldered prototype board with wires, and I hope I use it properly but they fail abnormally often.

When it fails, most often, the current fails to pass when the gate is at logic low. Sometimes it fails to stop the current from crossing the mosfet when the gate is high. But it never change. When it fails, it's either all the time open or all the time close, no matter what voltage is applied to the gate or elsewhere.

Now I read that the "Continuous drain current" is rated -0.17A. Is it possible that this P-MOSFET is for negative current? Negative on the drain means positive on the source, isn't it? Vds is also negative. But here again it's the voltage of the drain relative to source.

I don't understand the reason for the failures:

  • Outputs to S and G are between 0 and 5V (I don't think negative voltage may have appeared at these pins, but certainly not more than 5V.)

  • Outputs comes from IC's (for example 74HC595 shift register) or other MOSFET (N or P) (pull-up etc). It's difficult to give you a precise schematic because I noticed the failures in various situations. So let's consider the chemartic above. It's intended for CMOS logic.

  • Input is also an IC's (last I tried was 74HC595 shift register.) Here again, I can't confirm it failed only when linked on this ic. Just that I'm working with it now.

  • Resistor value is 140R. Sometimes I used without any resistor when I forget to put it. It doesn't seem related to the presence or absence of this resistor.

  • Sometimes it failed either immediately or never worked. Sometimes I have to replace it once or twice before it works.

  • When it works the circuit works as expected. Multiple times.

  • They often fail after I unsoldered and resoldered wires to the pins when making change on the prototype board. Visual inspection shows that the connection should be OK. I soldered countless SOT32 devices without any problem, including N-Mosfets.

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  • \$\begingroup\$ "Works as expected" -- What, exactly, is expected? \$\endgroup\$ – TimWescott Feb 16 at 16:27
  • \$\begingroup\$ @TimWescott That 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2. That 0V (or logic low) appears on U3 when there is logic high on U4 and logic high on U2 or logic low on U2 independantly of U4. \$\endgroup\$ – Fredled Feb 16 at 16:32
  • \$\begingroup\$ Please edit your question to reflect that, and describe the behavior that actually happens. The short answer is that what you want ain't gonna happen, for a variety of reasons. \$\endgroup\$ – TimWescott Feb 16 at 16:33
  • \$\begingroup\$ Most often the current fails to pass when the gate is at logic low, Sometimes it fails to stop when the gate is high. But it never change. When it fails, it's either all the time open or all the time close, no matter what voltage is applied to the gate or elsewhere. \$\endgroup\$ – Fredled Feb 16 at 16:35
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    \$\begingroup\$ @TimWescott I Added the comments above to the question. I'm eager to know the reason why it's not gonna happen but it happens after replacing the mosfet. \$\endgroup\$ – Fredled Feb 16 at 16:40
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The goal is that 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2. That 0V (or logic low) appears on U3 when there is logic high on U4 and logic high on U2 or logic low on U2 independently of U4

You are trying to use a P-FET to perform a logic function, and there is nothing wrong with the method, you just need to improve the implementation slightly.

Firstly, lets show a schematic to understand why the switch (logic) using the BSS84 is not acting as it should.

schematic

simulate this circuit – Schematic created using CircuitLab

  1. If U2=Hi and U4=Hi then the P-FET is OFF V(gs) = zero. But current still flows (essentially a constant current) because of I(DSS). For the BSS84 I(DSS) is 15uA maximum. While I(DSS) for your device is probably below 15uA, it would only take 6-7uA to register a Hi on U3. If you are hand soldering the FET in place it is easy to overheat it, and one of the side effects is to see a marked increase in leakage currents. In all probability overheating during soldering is the reason you see some of the FETs 'fail'.
  2. If U2 = Lo, then the input to U3 is held low because of the body diode and R2 irrespective of the logic level of U4.

I'd suggest the only problem you have is I(DSS), and you can solve this simply by reducing R2. If you dropped R2 to 50k Ohm, then you assure a low on U3 for leakage currents up to 20uA or so.

If you want to understand the leakage currents for small channel length devices such as the BSS84 you could read Chenming Hu's Modern Semiconductor Devices for Integrated Circuits Chapt 7

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  • \$\begingroup\$ Thank you very much for this reply. I'll try a lower value for R2. The temperature of my iron is set between 275 and less than 300C (no exact temperature displayed). I'll try 250C. There is also a possibility that the pins are very delicate mechanicaly. But that would be the first time for me. This part is maybe very sensitive and maybe not the best quality. It was one of the cheapest in this category. \$\endgroup\$ – Fredled Feb 16 at 21:07
  • \$\begingroup\$ @Fredled You should be able to solder with no more than 220C if you are using solder paste. Solder flow times should be less than 5 seconds. 300C is very high. \$\endgroup\$ – Jack Creasey Feb 16 at 21:58
  • \$\begingroup\$ I will try to lower the temperature. But then it's sometimes a bit slow on larger parts. I will test how cold I can solder this and turn the regulator left when I do this mosfet. \$\endgroup\$ – Fredled Feb 17 at 18:29
  • \$\begingroup\$ I think the problem is that the BSS84 is a FET but not a MOSFET. The transconductance is much smaller (0,13) compared to a MOSFET (2,6 or 5). I took the wrong part thought it was in the MOSFET category at the online vendor. \$\endgroup\$ – Fredled Feb 20 at 18:25
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Mosfets are highly sensitive to ESD/EOS on the gate terminal.

If M1 is wired with flying leads, I would add a zener across the gate/source terminals.

In a pinch, for 5V signally you can use the base-emitter junction of a small-signal transistor as a \$\simeq 7 \text{ V}\$ zener diode.

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    \$\begingroup\$ That's one possibility. Now I expect that when there is a pull-down resistor or the signal comes directly from an ic's output it shouldn't happend. But we never know. I'll try. Thanks. \$\endgroup\$ – Fredled Feb 16 at 17:16
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Refer to the part datasheet.

Given your description of the desired behavior of the circuit, there are several properties of CMOS gates and of MOSFETs that you misunderstand.

  • 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2.

This should happen. Your expected circuit behavior is consistent with turning the FET on by lowering the gate voltage to 4.5V or more below the source voltage. At that point, current should flow from gate to source.

  • That 0V (or logic low) appears on U3 when there is logic high on U4 and logic high on U2.

(Relevant to the original schematic that had no pull-down at the input to U3): This is neglecting the fact that in an ideal FET, the drain is high-impedance when it is off, and that a CMOS input is also high impedance. I would expect that if the source is at 5V (your U2) and the gate (your U4) goes from 0V to 5V, that the drain (U3) would stay high, but may or may not eventually wander down to some intermediate value, or it would pick up line-frequency hum.

  • That 0V (or logic low) appears on U3 when there is logic high on U4 and logic low on U2.

This neglects two things: first, that MOSFETs are fairly symmetrical beasts; and second, the body diode.

The only thing that prevents a MOSFET from reversing what acts like a source and what acts like a drain is how the substrate is connected. This is because the actual physical construction of most MOSFETs is symmetrical, or close to it (unlike junction transistors, which generally have big collectors and little emmitters -- but will still work in "reverse").

The other preventer is that there is a parasitic diode from drain to source. See the picture on the left edge of the first page of the datasheet, about 1/3 of the way down the page. This diode will conduct when the drain voltage (your U3 input) is higher than the source voltage (your U2 output). When U2 is at 0V and U3 is at 5V, I would expect U3 to get pulled low through that diode if U4 is high, or by FET action if U4 is low.

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  • \$\begingroup\$ " I would expect that if the source is at 5V (your U2) and the gate (your U4) goes from 0V to 5V, that the drain (U3) would stay high." usualy there is a 330K [ull-down resistor to ground to prevent that. \$\endgroup\$ – Fredled Feb 16 at 17:03
  • \$\begingroup\$ I don't understand the second part of your answer. How could U3 be at 5V if it's an input exclusively? \$\endgroup\$ – Fredled Feb 16 at 17:22
  • \$\begingroup\$ 1. Current flows from Source to Drain NOT Gate to Source 2. Logic high on U4 means that I(DSS) is in effect. This could be several uA and result in a high at U3. The 330k resistor should be dropped to 50k Ohm. \$\endgroup\$ – Jack Creasey Feb 16 at 17:52
  • \$\begingroup\$ How could U3 get pulled to anything but 5V if it starts out at 5V and isn't connected to anything? (Note that my original statement was based on the schematic without the pulldown at the drain of the FET). \$\endgroup\$ – TimWescott Feb 16 at 20:04
  • \$\begingroup\$ @TimWescott Thank you for your replies. It was very interresting too. Yes, I forgot to add it on the chematic. Sometimes I forget it in reality too. So the schematic was moreless exact. You confirmed that this was something that could happen. \$\endgroup\$ – Fredled Feb 16 at 21:10

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