Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity latch_rs is Generic (delay: time); Port ( R : in STD_LOGIC; S : in STD_LOGIC; Preset : in STD_LOGIC; Clear : in STD_LOGIC; Q : out STD_LOGIC; nQ : out STD_LOGIC); end latch_rs; architecture behavioral of latch_rs is signal Q1 : std_logic; signal Q2 : std_logic; begin proc : process (Preset, Clear, R, S) begin if (R='1') or (Clear='0') then Q1 <= '0' after delay; Q2 <= '1' after delay; elsif (S='1') or (Preset='1') then Q1 <= '1' after delay; Q2 <= '0' after delay; end if; end process; Q <= Q1; nQ <= Q2; end behavioral;
The problem is that during Post-Map simulation the feedback signals (Q and nQ) seems to be consumed by the and port: is this possible? And if so, how can I avoid this to happen? (the clear 0 sets nq to 1)
EDIT: During the Behavioral simulation the circuit is working fine.