# Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema:

Where the "latch_rs" is written as follow:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch_rs is
Generic (delay: time);
Port ( R  : in  STD_LOGIC;
S  : in  STD_LOGIC;
Preset : in STD_LOGIC;
Clear : in STD_LOGIC;
Q  : out  STD_LOGIC;
nQ : out  STD_LOGIC);
end latch_rs;

architecture behavioral of latch_rs is

signal Q1 : std_logic;
signal Q2 : std_logic;

begin

proc : process (Preset, Clear, R, S)
begin
if (R='1') or (Clear='0') then
Q1 <= '0' after delay;
Q2 <= '1' after delay;
elsif (S='1') or (Preset='1') then
Q1 <= '1' after delay;
Q2 <= '0' after delay;
end if;
end process;

Q <= Q1;
nQ <= Q2;

end behavioral;


The problem is that during Post-Map simulation the feedback signals (Q and nQ) seems to be consumed by the and port: is this possible? And if so, how can I avoid this to happen? (the clear 0 sets nq to 1)

EDIT: During the Behavioral simulation the circuit is working fine.

• "consumed"? I think it's more likely you made a mistake in your VHDL somewhere, but it's been too long since I worked with VHDL for me to be able to effectively help. – Hearth Feb 16 at 17:31
• @Hearth So the problem should't be the feedback ? Because in behavioral simulation the problem is not happening – PeppeDAlterio Feb 16 at 17:33
• try moving Q <= Q1; and nQ <= Q2; into the process block – jsotola Feb 16 at 19:29
• @jsotola While it's cleaner VHDL (and should be done), that won't change a thing during Post-Map simulation. – DonFusili Feb 18 at 10:09