Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema:

RTL Schema Where the "latch_rs" is written as follow:

library IEEE;

entity latch_rs is
    Generic (delay: time);
    Port ( R  : in  STD_LOGIC;
           S  : in  STD_LOGIC;
              Preset : in STD_LOGIC;
              Clear : in STD_LOGIC;
           Q  : out  STD_LOGIC;
           nQ : out  STD_LOGIC);
end latch_rs;

architecture behavioral of latch_rs is

signal Q1 : std_logic;
signal Q2 : std_logic;


proc : process (Preset, Clear, R, S)
        if (R='1') or (Clear='0') then 
            Q1 <= '0' after delay;
            Q2 <= '1' after delay;
        elsif (S='1') or (Preset='1') then
            Q1 <= '1' after delay;
            Q2 <= '0' after delay;
        end if;
    end process;

Q <= Q1;
nQ <= Q2;

end behavioral;

The problem is that during Post-Map simulation the feedback signals (Q and nQ) seems to be consumed by the and port: is this possible? And if so, how can I avoid this to happen? (the clear 0 sets nq to 1)

Post-map ISim

EDIT: During the Behavioral simulation the circuit is working fine.

  • 1
    \$\begingroup\$ "consumed"? I think it's more likely you made a mistake in your VHDL somewhere, but it's been too long since I worked with VHDL for me to be able to effectively help. \$\endgroup\$
    – Hearth
    Feb 16, 2019 at 17:31
  • \$\begingroup\$ @Hearth So the problem should't be the feedback ? Because in behavioral simulation the problem is not happening \$\endgroup\$ Feb 16, 2019 at 17:33
  • 1
    \$\begingroup\$ try moving Q <= Q1; and nQ <= Q2; into the process block \$\endgroup\$
    – jsotola
    Feb 16, 2019 at 19:29
  • \$\begingroup\$ @jsotola While it's cleaner VHDL (and should be done), that won't change a thing during Post-Map simulation. \$\endgroup\$
    – DonFusili
    Feb 18, 2019 at 10:09

1 Answer 1


This depends on your netlist.

You have a glitch (should be on S) somewhere, which propagates through S1 and is already compensated for the Q1 but not the Q2 at the time it reaches the latch implementation.

Regarding that beautiful latch:

Since you tag with Xilinx, you're probably synthesizing for FPGA's. These don't have latches but will generally infer a flip-flop with a multiplexer somewhere. That's in case of an RTL latch description though (for example a variable or signal that is changed on a clock flank but not reset). In order to try and conform to the delay nonsense, some tools will try to brute force this with buffer-LUTs. I'm not familiar enough with ISE (which you also tagged) anymore to know what its strategy will be there.


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