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What \$R_{on}\$ do I use to calculate the delay for an inverter gate? In my class we came up with two definitions of \$R_{on}\$, one for saturation and one for triode. Is there a certain mode I should assume for the transistor or do I need to calculate it by hand? I wasn't given a V_in though so I don't know how I'd be able to calculate the mode by hand. Am I missing something really obvious?

Drawing of the inverter: drawing of the inverter

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  • \$\begingroup\$ Hi Paula! Please tell us which component and circuit specifically you're talking about: Triodes have become quite... uncommon, so I might be missing what you're specifically referring to! \$\endgroup\$ – Marcus Müller Feb 16 at 19:35
  • \$\begingroup\$ This is for a theoretical thing, not really a real component. Should my question be in another stackExchange? I'll add a picture \$\endgroup\$ – Paula Feb 16 at 19:37
  • \$\begingroup\$ @MarcusMüller "triode mode" is an alternate name for the linear mode of a FET. \$\endgroup\$ – Hearth Feb 16 at 20:00
  • \$\begingroup\$ @Paula There's a built-in schematic editor in the question editor. \$\endgroup\$ – Hearth Feb 16 at 20:03
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Suppose we're talking about the falling transition time of an inverter. We assume that the PMOS transistor is completely cut off and that \$V_{GS}\$ for the NMOS is equal to the supply voltage. Now, for most of the range of voltages that the output will swing, from \$V_{DD}\$ to ground, \$V_{DS}\$ will be large enough that the NMOS will be in saturation. The real definition of "most" depends on the switching points that you use to define the "transition time"...20% to 80% of \$V_{DD}\$ is typical. So, the transition time for the output is mostly dependent on the \$I_{DS(sat)}\$, and it's only as the output voltage gets close to its final value that the triode region \$R_{DS}\$ becomes significant.

Of course, this is all just a rough approximation. The input transition time can not be ignored in practice. Your best answers will come from a good SPICE simulation.

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For standard logic, CMOS Vdd controls RdsOn (Ron), depending on T and Vdd tolerance with mfg tolerances. Pch FETs tend to be slightly larger as they channel Ron is higher slightly for the same size, so as to match them for complementary threshold and symmetrical slew rate.

CD4000 family was around 300 ohms +/- 50% measured by datasheet at various Vdd levels for Vol/Iol=Ron with Vgs(th)= +/-1.5V by design. The higher Vdd produces lower Ron. At one time it was well known in the 70's that Fairchild and Harris were faster than NSC, MOT were the slowest. This could have been due to lower RdsOn and/or lower Miller Cfb as all FETs have a somewhat constant Ron*C=T constant for a given Vds max with some major differences for power FETs.

For 5V logic families, the Ron is 50 to 66 (? AFAICR) Ohms +/- 50 % depending on temp and Vdd tolerance, by defacto design.

For 3.3V logic it is 25 Ohms +/- 50(?)% e.g. ARM chips

For 1.6V logic it is about the same, so each FET family has a controlled Vgs and Ron to prevent shootthru heat damage yet low Ron to produce a rated Slew Rate for a rated load capacitance.

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