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I was wondering what the output of capturing flop looks like, if there is a hold time violation from capture flop. Can anyone explain with a timing diagram?


marked as duplicate by Edgar Brown, Community Feb 25 at 19:31

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There are a few possibilities but can never predict with so much certainty as to be able to provide a reproducible scope shot. You see there are factors that influence the outcome of such event at the flip flop which include:

  1. Rise time of the clock signal
  2. How much the hold time is violated
  3. Noise in the signal lines to the flip-flop
  4. Noise level on the ground bus
  5. Noise on the Vdd/Vcc bus
  6. Loading in the flip-flop output
  7. Chip type of the flip-flop
  8. Stray circuit capacitance
  9. Circuit characteristics change when poking a scope probe to monitor the behavior

The flip flop output may exhibit one of these behaviors

  • The output may start to change state but then return to the pre-clock level
  • The output may change state normally even in the event of a spec violation
  • The output may go to some state where the voltage level goes to value part way between the Vdd and GND and stay there for a good amount of a clock cycle
  • The output may not change at all at the violation clock edge but then pickup the valid output level at the next clock edge.
  • \$\begingroup\$ Thanks for the reply. If you don't mind can you please explain in detail what cases the output of flipflop exhibit different cases as you mentioned or it might be any behavior as you mentioned in for a violation. \$\endgroup\$ – Pasupuleti Vinaykumar Feb 18 at 3:07
  • \$\begingroup\$ @PasupuletiVinaykumar - No I cannot explain it. There are too many variables and thus the heart of the answer above. If you have an all fired interest in a particular part in a specific set of conditions then you should setup a testing fixture and make measurements. From that you will learn good things about that scenario. Would the same learnings apply to other part types in different conditions - Most likely not !! \$\endgroup\$ – Michael Karas Feb 18 at 3:22

Some years ago, we used a 0-2ns variable delay line to see what happened when we cut too close to specs. Our chip was the venerable 7474 D-flop. By attaching the delay line to the input or the clock, we found that under some conditions, the output would "ring". The result was an output waveform that looked like a bouncing ball; instead of a clean digital square-wave, the signal looked like a sine wave. It hit a peak, decayed to near ground, hit a second peak, lower than the first, and so on until, several milliseconds later, it settled into the ground state. It was a trace that looked like a bouncing ball. I used to have a photo from the oscilloscope camera, but I have no idea how I'd find it today. The problem was one of synchronizing two signals, generated independently. One was a clock signal to latch the input data, generated from the internal logic, and the other was a data signal from an outside source. I have also forgotten how the hardware people solved this (I was a software guy on the project).


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