I know of two circuits which can act as edge detector:

  1. A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with another enter image description here enter image description here

  2. A clock and its inverted output connected to AND gate. enter image description here

Respective images are pulses generated for a given square wave.

Which one of them is more prevalent and versatile in logic design ? because in books only 2nd is used for synchronising outputs.

I think RC circuit helps us to adjust duration of the pulse so it is better.

  • \$\begingroup\$ Define "better". \$\endgroup\$ – Hearth Feb 17 '19 at 17:46
  • \$\begingroup\$ I desire a general comparison between advantages and disadvantages of both \$\endgroup\$ – Shlok Vaibhav Feb 17 '19 at 18:16

The answer is none of the above, both of them, and it depends on the application.

The RC solution has a strong dependency on signal slew rate, loads its input, and might not be adequate for logic-level circuitry, while being perfectly fine to trigger a 555 and some mostly-analog applications.

The gate solution is rather common to generate a glitch in logic circuits, with pulse-width being tuned by either adding inverters in the chain, adding capacitance to the nodes, or tuning the characteristics of the inverters.

As anything in engineering, the RC solution is good enough in many cases. If you need to add some constraints to it (e.g., independence of input slew rate, independence of source impedance, guaranteed pulse voltage, reliable pulse width) you will soon find that it becomes too complicated to be practical, so variants of the gate solution become more practical.

You will exclusively find variants of the gate solution implemented inside logic ICs. I’ve used relatively long chains of purposefully slow inverters to provide carefully sequenced guaranteed-reliable asynchronous pulses to operate IC-wide logic after an input event with 100MHz interface clocks. Given that the width of the pulses scales with the speed of the logic inside the IC, this solution is guaranteed to work for all performance corners of the technology.

  • \$\begingroup\$ Thanks , but due to my low reputation I can't upvote \$\endgroup\$ – Shlok Vaibhav Feb 17 '19 at 19:24

I don't want to sound like a racist, but your second example is a classic "race condition" that would cause an undergrad in a digital design course to get a 0% for the answer. The propagation delay through the inverter will likely cause either setup or hold time of the AND/NAND gate to be violated, resulting in an unstable circuit. Forget any design that looks like this. Prop delay is temperature-dependent, and what works on your little breadboard circuit won't necessarily work when it is in its final configuration in a closed box in a warm room.

Why do you need a positive edge detector? If we know the reason, it might simplify designing a circuit to fit your needs.

  • \$\begingroup\$ Every single designer that has ever put together an edge-triggered flip flop would disagree with you. As well as anyone that has ever designed any asynchronous logic domain. It is only a “race condition” if you don’t know what you are doing. \$\endgroup\$ – Edgar Brown Feb 18 '19 at 0:58

I don't think either of these circuits would be used in practice. I would use a flip-flop as a synchronous edge detector.

EDIT: Each of these circuits provides a pulse that is highly dependent on poorly controlled characteristics of the circuit. The tolerances of resistors and capacitors are fairly large, and the delay through an inverter varies significantly with supply voltage and temperature.

Neither circuit is readily synthesizable in an FPGA or ASIC. They are both hacks.

  • \$\begingroup\$ Do you mean they are just used to give an idea of what happens in easy terms to first year undergraduates ? \$\endgroup\$ – Shlok Vaibhav Feb 17 '19 at 19:19
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    \$\begingroup\$ The gate delay edge detector is widely used. While it may be less likely to use this in an FPGA or ASIC development with synchronous clocking domains, this was a tried and true technique for edge detection in asynchronous systems based on 74xx logic. \$\endgroup\$ – Jack Creasey Feb 17 '19 at 22:20
  • \$\begingroup\$ Quite the opposite, within an IC the most accurate way to match the propagation delay of a set of gates is to use another set of gates. Even though different die would have faster or slower characteristics, all of the gates in one die would be relatively well-matched. You just have to know what you are doing. I have never had a yield issue from this type of circuits. \$\endgroup\$ – Edgar Brown Feb 18 '19 at 1:03
  • \$\begingroup\$ @EdgarBrown Yes, you can match gate delay to gate delay, but if you need to match a pulse width to a synchronous clock you will have trouble. You can overspecify the number of gates used to generate the delay but then you run the risk of creating a pulse that is two clocks wide under slow conditions. You don't even have individual gates like this in an FPGA, so a series string of inverters will be optimized to a single inverter, which will then be folded into a LUT. It's just not a robust way to do synchronous design. \$\endgroup\$ – Elliot Alderson Feb 18 '19 at 2:10
  • \$\begingroup\$ @EdgarBrown Yes, I agree. I have done things like this in the bad old days when doing board-level 74xx designs. But not anymore, not for synchronous designs when trying to avoid metastability. \$\endgroup\$ – Elliot Alderson Feb 18 '19 at 2:12

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