The answer is none of the above, both of them, and it depends on the application.
The RC solution has a strong dependency on signal slew rate, loads its input, and might not be adequate for logic-level circuitry, while being perfectly fine to trigger a 555 and some mostly-analog applications.
The gate solution is rather common to generate a glitch in logic circuits, with pulse-width being tuned by either adding inverters in the chain, adding capacitance to the nodes, or tuning the characteristics of the inverters.
As anything in engineering, the RC solution is good enough in many cases. If you need to add some constraints to it (e.g., independence of input slew rate, independence of source impedance, guaranteed pulse voltage, reliable pulse width) you will soon find that it becomes too complicated to be practical, so variants of the gate solution become more practical.
You will exclusively find variants of the gate solution implemented inside logic ICs. I’ve used relatively long chains of purposefully slow inverters to provide carefully sequenced guaranteed-reliable asynchronous pulses to operate IC-wide logic after an input event with 100MHz interface clocks. Given that the width of the pulses scales with the speed of the logic inside the IC, this solution is guaranteed to work for all performance corners of the technology.