I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (let me know if there is any!)
I suppose Timing Analyzer should give some value of Fmax for Fast Models as well.
BTW, Does Xilinx's Vivado let the designer know about feasible Fmax values for Slow/Fast Models in timing reports?
It's been a while using vivado, I remember it gives more importance to worst Negative Slack (WNS).