I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (let me know if there is any!)

I suppose Timing Analyzer should give some value of Fmax for Fast Models as well.

BTW, Does Xilinx's Vivado let the designer know about feasible Fmax values for Slow/Fast Models in timing reports?

It's been a while using vivado, I remember it gives more importance to worst Negative Slack (WNS).

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    \$\begingroup\$ Does Xilinx's software support their competitors' devices? I would have thought you'd have to be using Intel/Altera's software for an Intel/Altera part. \$\endgroup\$ – Hearth Feb 17 at 18:33
  • \$\begingroup\$ @hearth I am using Intel/altera's software. Xilinx doesn't support intelfpga. My question was for Intel FPGA only. Xilinx Vivado query is separate query out of curiosity. \$\endgroup\$ – Sourabh Tapas Feb 18 at 16:31
  • \$\begingroup\$ If it's a separate query, it should be a separate question. You're allowed to post two questions, no one will get mad! \$\endgroup\$ – Hearth Feb 18 at 17:13

Timing analysis is for checking for worst-case timing issues.

For the clock period (setup time), you're interested in the worst case paths, the paths with the longest delay during the worst possible (slowest) operating conditions. This requires the slow model.

For hold time, you're interested in the worst case paths as well, but in this case you're looking at the shortest path, the paths with the shortest delay during the worst possible (fastest) operating conditions. This requires the fast model.

Checking setup times on the fast model or hold times on the slow model won't give you any meaningful information, because they are not the worst-case conditions for those checks.

Edit: to your question on Vivado, it shows all of the standard timing information (worst/total negative slack, worst/total hold slack, worst/total pulse width slack) but it does not separate these out by fast model/slow model, it simply uses the appropriate model for each measurement.


The actual, real-life, maximum operating frequency of your circuit is limited by its behavior with slow models. Giving you a number for fmax with fast models would be misleading.

You need the fast models to look for hold time violations.

  • \$\begingroup\$ Ok. I get your point. But, it could have provided an indicative fmax for fast model corner case. Anyway thanks for knowledge. It was difficult to ask google. \$\endgroup\$ – Sourabh Tapas Feb 18 at 16:40

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