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I'm trying to implement function call after having timeroverflow or comparison of counter registers.

Chip: SAM4E

tc_init(TC0, 2, TC_CMR_TCCLKS_TIMER_CLOCK3);
tc_write_rc(TC0, 2, 750000);
tc_enable_interrupt(TC0,2,TC_IER_COVFS | TC_IER_CPCS);

NVIC_DisableIRQ(TC2_IRQn);
NVIC_ClearPendingIRQ(TC2_IRQn);
NVIC_SetPriority(TC2_IRQn, 0);
NVIC_EnableIRQ(TC2_IRQn);


tc_start(TC0,2);

I tried many codes that didn't work. I had to switch to TC0 so I could see the timer value actually changing:

(TC0->TC_CHANNEL[2].TC_CV)

void TC2_Handler(void)
{
    ii++;
}

unfortunately this code doesn't work. (it has a bug that goes to infinite loop).

i can see timer value changing with this code but there is no interrupt handler working:

 sysclk_enable_peripheral_clock(ID_TC2);

tc_init(TC0, 2, TC_CMR_TCCLKS_TIMER_CLOCK3);
tc_write_rc(TC0, 2, 75000);
tc_enable_interrupt(TC0,2, TC_IER_COVFS  );

NVIC_DisableIRQ(TC2_IRQn);
NVIC_ClearPendingIRQ(TC2_IRQn);
NVIC_SetPriority(TC2_IRQn, 0);
NVIC_EnableIRQ(TC2_IRQn);


tc_start(TC0,2);

why is this not correct code?
why 'TC_IER_COVFS' doesn't trigger TC2_handler(). and it does not work also. (although i can see timer started)...
why 'TC_IER_CPCS' trigger fault ( i guess it goes to dummy_handler!).
what would be the correct way to fix this

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  • \$\begingroup\$ Apart from that your question isn't Electrical Engineering related: Where in your software do you tell the build tool that "TC2_Handler" shall be your ISR? \$\endgroup\$ – mic Feb 18 at 7:46
  • \$\begingroup\$ @mic, i though its microcontrollers and embedded system is electronics related. electronics is electrical related. yeah i know that electrical is too wide but isnt electrical is where everybody post electrical / electronics? \$\endgroup\$ – Hasan alattar Feb 18 at 7:50
  • \$\begingroup\$ @mic yes, its ASF code, attribute ((section(".vectors"))) const DeviceVectors exception_table = { /* Configure Initial Stack Pointer, using linker-generated symbols / (void) (&_estack), (void*) Reset_Handler, (void*) NMI_Handler, (void*) HardFault_Handler, ....... (void*) TC2_Handler, \$\endgroup\$ – Hasan alattar Feb 18 at 7:56
  • \$\begingroup\$ @Hasanalattar, nope, if it's a primarily a programming problem, you'd go to Stackoverflow.com. However, this might be specific to hardware, so at least marginally on-topic. However, you've forgot to ask a specific question, so we've got nothing to answer! \$\endgroup\$ – Marcus Müller Feb 18 at 8:15
  • \$\begingroup\$ @mic Firmware for microcontrollers ("bare-metal"/RTOS) is explicitly on-topic. electronics.stackexchange.com/help/on-topic \$\endgroup\$ – Lundin Feb 18 at 11:41
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unfortunately this code doesn't work. (it has a bug that goes to infinite loop).

It is not an infinite loop: you do not clear the interrupt bit so when you return the interrupt is still pending and it goes back into the service routine.

I found some code I wrote a time ago for the SAM:

void TC0_Handler(void)
{ uint32_t dummy_sr;
  // must read status register to clear interrupt
  // This is unfortunately not (clearly?) mention in the datasheet
  dummy_sr = TC0->TC_CHANNEL[0].TC_SR;  

  // If we are running in one-shot mode disable the timer
  if (one_shot)
     TC0->TC_CHANNEL[0].TC_CCR = TC_CCR_CLKDIS;

  // Call the call back function
  (*t0_handler)();

}  // TC0_Handler
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  • \$\begingroup\$ thanks, it seems like i've to set (TC_CMR_CPCTRG) when i run tc_init. i tried to find that i've to clear TC_SR still didnt find it yet althougth it works now i've to run more tests. \$\endgroup\$ – Hasan alattar Feb 18 at 15:08
  • \$\begingroup\$ "i tried to find that i've to clear TC_SR still didnt find it " If I recall, I read the SR because most CPU's requires that and it started to work. Later I came across it somewhere . It explains my comment in the code :-) \$\endgroup\$ – Oldfart Feb 18 at 15:38
  • \$\begingroup\$ hello, i want to put this as an answer, although 2 more points (why TC_IER_COVFS is not triggering the isr function) and why (tc1 and tc2 are not triggering also) .. not channels but the 3 timers/counters them self? \$\endgroup\$ – Hasan alattar Feb 19 at 15:12
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    \$\begingroup\$ @Hasanalattar Just let it be. I am not doing this for the points. \$\endgroup\$ – Oldfart Feb 19 at 15:33
  • \$\begingroup\$ the COVFS was triggering the ISR, however it takes 6hrs to reach to overflow value (12MHz XTAL -> SCLK PRES 2 -> TCCLK /32 ) = (2^32)/187500 / 3600sec = 6.36 Hours \$\endgroup\$ – Hasan alattar Mar 19 at 12:42

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