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The first image is the push-pull configuration. Current is drained to GND through the PMOS and NMOS

The second image is the pull-up configuration Current is drained to GND through the large resistor

The only real differences i see are that for the first configuration, higher current will be drawn and for the second configuration less current will be drawn from the power supply to ground. And this is given that there is a HIGH and a LOW signal to the gates.

Does this smaller current affect the transition time from a HIGH to a LOW or LOW to a HIGH registered at the output?

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  • \$\begingroup\$ Ha, I recognize the 3rd circuit ;-) I drew it. \$\endgroup\$ – Bimpelrekkie Feb 18 at 14:30
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Assuming all transistors (NMOS and PMOS) behave in an equal way under similar circumstances (deliver the same drain current for a given Vgs) then you're right, the configurations with the pull up resistor draw less supply current.

The first circuit is btw something we generally do not use / want to avoid as it basically "shorts" the supply. What is done is that extra transistors are added (in series with the ones that are drawn in your circuit) which will enable / disable each inverter. Then only one inverter is allowed to be enabled at a given moment. What I refer to is called a tri-state output, besides 0 (zero), 1 (one) it also has a third state: high-Z or open.

Does this smaller current affect the transition time from a HIGH to a LOW or LOW to a HIGH registered at the output?

Yes it does.

Imagine there is some capacitance (the input capacitance of the following circuits) connected, for a low to high transition, that capacitor will be charged more slowly when it has to charge through the pull-up resistor compared to the situation where a PMOS (which can provide more charging current) is used. There will always be some capacitance even if you would connect nothing to the output there are still the drain-source capacitances of the transistors present.

That is assuming the PMOS would deliver more current compared to the resistor but that will be the case anyway. If not then the resistor would need to have a very low value and the NMOS transistors would not be able to pull the output low.

For the high to low transition, the difference (compared to a PMOS/NMOS output) will be small as the capacitance will be about the same and in both cases an NMOS discharges the capacitor.

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In the first image, one or both conduction mosfets will probably blow because it draws too much current. The current is defined by the Rdson's of both conduction mosfets.

The resistor in the second image will only affect the transient time if the output is loaded with a capacitance which is almost always the case. E.g. the gate capacitance of a (not drawn) mosfet that 'senses' the output.

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