I'm designing a PCI Express board with an Artix-7 from Xilinx. I'm reading through the PCIe block description and on page 199 it says:
Section 6.6 of PCI Express Base Specification, rev 1.1 states “A system must guarantee that all components intended to be software visible at boot time are ready to receive Configuration Requests within 100 ms of the end of Fundamental Reset at the Root Complex.”
This is fine. It seems I can easily sequence the power supplies and config the FPGA in 100ms, but I'd like to understand how much time I have anyway.
Section 2.6.2 of the PCI Express Card Electromechanical Specification, v1.1 [Ref 2] defines TPVPREL as a minimum of 100 ms, indicating that from the time power is stable the system reset is asserted for at least 100 ms
Lastly, on page 201 it says:
Figure 3-92 shows that power is valid before PWR_OK is asserted High. This is represented by T3 and is the PWR_OK delay. The ATX 12V Power Supply Design Guide defines PWR_OK as 100 ms < T3 < 500 ms, indicating that from the point at which the power level reaches 95% of nominal, there is a minimum of at least 100 ms but no more than 500 ms of delay before PWR_OK is asserted. Remember, according to the PCI Express Card Electromechanical Specification [Ref 2], the PERST# is guaranteed to be asserted a minimum of 100 ms from when power is stable indicated in an ATX system by the assertion of PWR_OK.
So it seems I should have at lest 300ms from when the power is within 95% of nominal:
- 100ms until PWR_OK - TPWRVLD
- 100ms from PWR_OK to end of PERST# - TPVPERL
- and then finally I have to be ready to respond 100ms after end of PERST#.
However, Equation 3-1 in the document says:
FPGA Configuration Time ≤ TPWRVLD + TPVPERL
What am I missing?