I'm designing an op amp integrator with a 100nF capacitor, and need to include a logic level reset/discharge option. I would like to use the DG467 analog switch due to its low cost and small package, however I am concerned about the current rating and on resistance.

Worst-case: the capacitor has the full 10V supply voltage across its terminals (this would only happen in a fault condition), the reset switch is turned on. According to LTspice, the capacitor would discharge in ~10μs, assuming that the switch has a 10Ω on resistance. This will produce a 1A pulse, 10x the "absolute maximum rating" (100mA for 1ms pulsed with a 10% duty cycle).

My question: is a fast (i.e. less than 10μs) 1A pulse likely to destroy the switch? Is it necessary to add a 100Ω series resistance in order to keep the current less than 100mA, and thus increasing the discharge time to 100μs?

  • \$\begingroup\$ I would add the resistor. You could also add a reset transistor if you want, so you can reset it independently with a discrete transistor. Pay attention to the leakage currents and whatnot to make sure it will not adversely effect your integration result. \$\endgroup\$
    – user57037
    Feb 18, 2019 at 20:21
  • 1
    \$\begingroup\$ Note that the (positive) supply voltage of the DG467 should be at least 10V at the time you want to short the cap (according ABSOLUTE MAXIMUM RATINGS VCOM < (V+) + 2 \$\endgroup\$
    – Huisman
    Feb 18, 2019 at 20:30

2 Answers 2


There is an absolute maximum of 100mA 10ms that you must not exceed.

I believe this is based on ampacity before fusing the xx nm CMOS junction by exceeding the current density.

\$E=0.5CV² = 0.5 * 0.1uF * (10V)² = 500uJ \$

Although the discharge energy is much lower than ESD. e.g. \$ESD = 1kV @ 100pF = 0.5 * 100pF * (1kV)² = 50 mJ\$
This is conducted in the ESD Diodes, not the CMOS junctions.

There is no good reason for exceeding ABS. MAX levels.

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The wirebonds are a little more robust and use AW-29 or 29 μm wire.

Design Changes:

  • define specs. for better choices, you don't need 0.1uF
  • reduce your cap value by 1~2 orders of magnitude
  • reduce your signal input current (increase R) to maintain dV/dt by 1~2 orders of magnitude
  • reduce the input bias of your Op Amp selection by >= 2 orders of magnitude or acceptable level
  • reduce your input offset to the acceptable level = TBD
  • never use ceramic caps unless C0G type ( memory effect is bad for S&H and I&D mode) instead use a film cap. ( any plastic)
  • measure logic dV/dt crosstalk between signal and logic input to minimize stray capacitance with 3mil gnd. guard tracks on either coplanar side of logic signal or reduce slew rate.

Parts often survive excursions beyond their absolute maximum ratings, but it's bad form to count on it. If you put in the resistor it looks like you'll be in spec for both current and time.


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