Noise margins logic circuits

Question

The noise margin is the difference between the min input HIGH and min output HIGH. What is the significance of it? Lets say the input HIGH voltage is currently 2.8V, a noise spike of -0.5V would still be a logic HIGH?

Answer 1

With all logic families having finite bandwidth, because of charge stored in the devices and on the metallization on the silicon, your noise margin thinking must consider the product of Time * Voltage. Or if you prefer, Time * Current.

Consider the simple inverter (6 in a package). Those inverters often are THREE cascaded inverters, the first of small input gate area so as to minimally load the incoming signal, then a larger inverter, then a very large inverter to handle 10pF or 100pF load capacitances (read the datasheets).

This inverter has TWO internal nodes, and those act as "filters" to prevent response to extremely narrow pulses.

This is consistent with the Time * Voltage model of noise immunity.

Answer 2

The noise margin is as you have shown in the diagram. Do be aware that a diagram such as this would be much better to place the output data on the left side and the input data on the right side. This way the data flow is more like how we would envision a schematic where circuit flow should would be from left to right.

The noise margin covers several cases as follows (using your diagram numbers).

1. For the logic 0 noise margin any noise spikes that appear coupled directly onto to the signal line of the driver can be up to 0.4V above the guaranteed output low level of the driver output before the receiver parts input gets pushed into the intermediate zone and potentially cause a problem in the receiver.
2. For the logic 1 noise margin any noise spikes that appear coupled directly onto to the signal line of the driver can be up to 0.4V below the guaranteed output high level of the driver output before the receiver parts input gets pushed into the intermediate zone and potentially cause a problem in the receiver.
3. For a localized ground noise spike at the receiver that appears as a spike above the ground level as referenced back to the driver the receiver interpretation of the input signal will remain valid as long as such ground level spike does not go above 0.4V.
4. To a lesser degree for many logic families, a localized VDD noise spike at the receiver that appears as a spike below the VDD level as referenced back to the driver VDD will remain valid as long as the VDD level spike does not go below 0.4V. (I say to a lesser degree because many logic parts high level thresholds are not so sensitive to the positive supply voltage level, especially for bipolar logic families. CMOS parts are a bit more power supply sensitive but at the same time often have greater high level noise margin).

Answer 3

For any logic family, there is no one simple number that defines its noise margin. Because of this, you usually cannot use a single noise margin number to compare the relative noise immunities of different families without a small pile of conditions and disclaimers.

The general idea is to quantify how much noise added to a theoretically pure signal a device can handle at its input without giving a false output. There are actually two noise margins, one each for high and low inputs.

The noise margin changes depending on the signal source. Let's say an input stage needs a minimum of 3.0 V to guarantee a (whatever) output. If the signal source makes a nominal 4.0 V output, that is a 1.0 V margin. If it makes a 5.0 V nominal output, that is a 2.0 V margin.

In the 70's, it was pretty safe to assume that a TTL input stage was almost always driven by some other TTL output stage. Same for CMOS. In that context, you could use the output stage's specs to define the noise margin for that input. Today that is nowhere near as sure a bet, so the noise margin must be evaluated within the system parameters, not just the device parameters.

Answer 4

If Vdd is 2.8V and the temperature and IC threshold tolerance just "happens to be" 50% Vdd {+/-15%} Injecting a -0.5 V spike may or may not cause an output transition. It depends on the source impedance and input actual threshold in that 30% process and temperature margin.

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Although there are over 30 Logic Families with various supply voltage ranges, speeds, impedance and thresholds, I would like to describe them as 3 common generic logic families, as follows;

TTL power gain (=10) logic with asymmetric current and voltage but symmetrical logic power noise margin.

CMOS Voltage gain logic ( Av=10 min unbuffered at Vdd min at max temp)

ECL, LVPECL, CML 50 Ohm differential current mode logic 10ps rise time, low EMI. Emitter-Coupled and Current Mode Logic (CML) uses constant current, GHz logic.

STSCL , "Sub-Threshold Source-Coupled Logic" , or just SCL , new family, faster like Emitter-coupled at low Vt levels.

The logic families are designed for symmetrical noise power margin immunity because noise is random polarity but defined with a spectral noise power.

Static Noise margin is NOT just OUT-IN Voltage margin. It is designed for Noise Power margin. TTL has a symmetrical input and output threshold of 1.4Vdc (0.8~2.0) where logic "0" was originally based on 2 PN junction drops but the "1" output voltage swing was increased to reduce the current & power consumption but the current rises near the switching threshold to present a lower impedance to stray noise and thus attenuate it.

CMOS having NMOS and PMOS were designed to match Vt and Ron characteristics but these shift with temperature, so the voltage margin rule might be applied here but it becomes asymmetrical with temperature shift of the input threshold.

You will see some reports showing voltage margin for different families but this is invalid for radiated noise margin but valid for supply and ground noise spikes.

Why not for radiated noise??

5V CMOS logic is roughly 50~66 Ohms driver Ron and 3.3V 74ALC' CMOS logic is roughly 25 Ohms (Vol/Iol=Ron) by design. ( with 25% tolerance) So although the voltage margin decreases, the current margin increases. \$V_{margin}^2/R_{on}=P_{margin}\$ Thus the concept that of pure voltage margin depends on where the noise comes from and it's source impedance.

Noise Margin
--              VOH     VIH     Margin  VIL    VOL      Margin
TTL [5volt]     2.4v    2.0v    400mV   0.8v    0.5v    300mV
FCT [5volt]     2.5v    2.0v    500mV   0.8v    0.5v    300mV
BTL [5 volt]    2.1v    1.62v   480mV   1.47v   1.1v    370mV
GTL [5 volt]    1.5v    1.05v   450mV   0.95v   0.55v   400mV
CMOS [5 volt]   4.9v    3.85v   1050mV  1.35v   0.1     1340mV
LVTTL [3volt]   2.4v    2.0v    400mV   0.8v    0.4v    400mV
LVCMOS [3 volt] 2.8v    2.0v    800mV   0.8v    0.2v    600mV
CMOS [2.5v]     2.0v    1.7v    300mV   0.7v    0.4v    300mV
CMOS [1.8v]     1.35v   1.1v    250mV   0.66v   0.45v   210mV

For crosstalk and radiated noise the impedance is high so it can be modelled by E field [V/m] and capacitance [pF] or E field V/m] and unbalanced CM impedance [Ohms] with respect to ground.

For ground shift noise the voltage but also the impedance is mucher lower. For TTL decoupling caps of 1 per 10 IC's was recommended, but since CMOS is a switched capacitance, 1 per IC is recommended depending on layout and IC size with 100nF to 300nF per IC to attenuate the switched internal and load capacitance current, Ic=CdV/dt.

Although MOS Ron depends on (Vgs-Vt) but near the midpoint threshold both NMOS and PMOS FETs are conducting, so the driver impedance may be a slightly lower which is the attenuating factor for radiated noise ingress attenuation, but also becomes a source of egress noise if not bypassed.